LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 374

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 316. USB Device Address register in device mode (DEVICEADDR - address 0x4000 6154) bit description
<Document ID>
User manual
Bit
23:0
24
31:25 USBADR
Symbol
-
USBADRA
20.6.7.1 Device mode
20.6.7.2 Host mode
20.6.7 Device address (DEVICEADDR - device) and Periodic List Base
Value Description
0
1
Table 315. Number of bits used for the frame list index
(PERIODICLISTBASE- host) registers
The upper seven bits of this register represent the device address. After any controller
reset or a USB reset, the device address is set to the default address (0). The default
address will match all incoming addresses. Software shall reprogram the address after
receiving a SET_ADDRESS descriptor.
The USBADRA bit is used to accelerate the SET_ADDRESS sequence by allowing the
DCD to preset the USBADR register bits before the status phase of the SET_ADDRESS
descriptor.
This 32-bit register contains the beginning address of the Periodic Frame List in the
system memory. The host controller driver (HCD) loads this register prior to starting the
schedule execution by the Host Controller. The memory structure referenced by this
USBCMD
bit 15
1
1
1
Reserved
Device address advance
Any write to USBADR are instantaneous.
When the user writes a one to this bit at the same time or before USBADR
is written, the write to USBADR fields is staged and held in a hidden
register. After an IN occurs on endpoint 0 and is acknowledged, USBADR
will be loaded from the holding register.
Hardware will automatically clear this bit on the following conditions:
Remark: After the status phase of the SET_ADDRESS descriptor, the
DCD has 2 ms to program the USBADR field. This mechanism will ensure
this specification is met when the DCD can not write the device address
within 2 ms from the SET_ADDRESS status phase. If the DCD writes the
USBADR with USBADRA=1 after the SET_ADDRESS data phase (before
the prime of the status phase), the USBADR will be programmed instantly
at the correct time and meet the 2 ms USB requirement.
USB device address
•
•
•
IN is ACKed to endpoint 0. USBADR is updated from the staging
register.
OUT/SETUP occurs on endpoint 0. USBADR is not updated.
Device reset occurs. USBADR is set to 0.
USBCMD
bit 3
0
1
1
All information provided in this document is subject to legal disclaimers.
USBCMD
bit 2
1
0
1
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Frame list size
32 elements (128 bytes)
16 elements (64 bytes)
8 elements (32 bytes)
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
N
7
6
5
374 of 1164
Access
-
R/W