LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 846

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.7.3.7 Updating a transmit object
36.7.3.8 Configuration of a receive object
Table 795. Initialization of a transmit object
The Arbitration Registers (ID28:0 and XTD bit) are given by the application. They define
the identifier and the type of the outgoing message. If an 11-bit Identifier (“Standard
Frame”) is used, it is programmed to ID28. In this case ID18, ID17 to ID0 can be
disregarded.
If the TXIE bit is set, the INTPND bit will be set after a successful transmission of the
Message Object.
If the RMTEN bit is set, a matching received Remote Frame will cause the TXRQST bit to
be set, and the Remote Frame will autonomously be answered by a Data Frame.
The Data Registers (DLC3:0, Data0:7) are given by the application. TXRQST and RMTEN
may not be set before the data is valid.
The Mask Registers (Msk28-0, UMASK, MXTD, and MDIR bits) may be used
(UMASK=’1’) to allow groups of Remote Frames with similar identifiers to set the TXRQST
bit. For details see
The CPU may update the data bytes of a Transmit Object any time via the IFx Interface
registers. Neither MSGVAL nor TXRQST have to be reset before the update.
Even if only a part of the data bytes are to be updated, all four bytes of the corresponding
IFx Data A Register or IFx Data B Register have to be valid before the content of that
register is transferred to the Message Object. Either the CPU has to write all four bytes
into the IFx Data Register or the Message Object is transferred to the IFx Data Register
before the CPU writes the new data bytes.
When only the (eight) data bytes are updated, first 0x0087 is written to the Command
Mask Register. Then the number of the Message Object is written to the Command
Request Register, concurrently updating the data bytes and setting TXRQST.
To prevent the reset of TXRQST at the end of a transmission that may already be in
progress while the data is updated, NEWDAT has to be set together with TXRQST. For
details see
When NEWDAT is set together with TXRQST, NEWDAT will be reset as soon as the new
transmission has started.
Table 796
Table
MSGVAL
MSGLST
1
0
761)
shows how a receive object should be initialized by software (see also
Section
Arbitration
application
dependent
All information provided in this document is subject to legal disclaimers.
RXIE
bits
0
Section
36.7.3.3.
Rev. 00.13 — 20 July 2011
application
dependent
application
dependent
36.7.3.4.2. The DIR bit should not be masked.
Data bits
TXIE
application
dependent
Mask bits
INTPND
0
application
dependent
RMTEN
EOB
1
Chapter 36: LPC18xx C_CAN
DIR
1
UM10430
© NXP B.V. 2011. All rights reserved.
TXRQST
0
NEWDAT
846 of 1164
0