LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 554

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
23.6.8 Interrupt Mask register
23.6.9 Raw Interrupt Status register
The INTMSK register controls whether various LCD interrupts occur.Setting bits in this
register enables the corresponding raw interrupt INTRAW status bit values to be passed
to the INTSTAT register for processing as interrupts.
Table 463. Interrupt Mask register (INTMSK, address 0x4000 801C) bit description
The INTRAW register contains status flags for various LCD controller events. These flags
can generate an interrupts if enabled by mask bits in the INTMSK register.
Table 464. Raw Interrupt Status register (INTRAW, address 0x4000 8020) bit description
Bits
0
1
2
3
4
31:5
Bits
0
1
2
Function
-
FUFIM
LNBUIM
VCOMPIM
BERIM
-
Function
-
FUFRIS
LNBURIS
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
FIFO underflow interrupt enable.
0: The FIFO underflow interrupt is disabled.
1: Interrupt will be generated when the FIFO underflows.
LCD next base address update interrupt enable.
0: The base address update interrupt is disabled.
1: Interrupt will be generated when the LCD base address
registers have been updated from the next address registers.
Vertical compare interrupt enable.
0: The vertical compare time interrupt is disabled.
1: Interrupt will be generated when the vertical compare time (as
defined by LcdVComp field in the CTRL register) is reached.
AHB master error interrupt enable.
0: The AHB Master error interrupt is disabled.
1: Interrupt will be generated when an AHB Master error occurs.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
FIFO underflow raw interrupt status.
Set when either the upper or lower DMA FIFOs have been read
accessed when empty causing an underflow condition to occur.
Generates an interrupt if the FUFIM bit in the INTMSK register is
set.
LCD next address base update raw interrupt status.
Mode dependent. Set when the current base address registers
have been successfully updated by the next address registers.
Signifies that a new next address can be loaded if double
buffering is in use.
Generates an interrupt if the LNBUIM bit in the INTMSK register
is set.
Chapter 23: LPC18xx LCD
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
-
0x0
0x0
0x0
0x0
-
Reset
value
-
0x0