LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 721

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
32.5.8 UART Line Status Register
Table 672. UART Line Control Register (LCR - addresses 0x4008 100C (UART0), 0x400C
The LSR is a Read Only register that provides status information on the UART TX and RX
blocks.
Table 673. UART Line Status Register Read Only (LSR - addresses 0x4008 1014 (UART0),
Bit
3
5:4
6
7
31:
8
Bit Symbol
0
1
OE
RDR
Symbol Value Description
PE
PS
BC
DLAB
-
100C (UART2), 0x400C 200C (UART3)) bit description
0x400C 1014 (UART2), 0x400C 2014 (UART3) ) bit description
0
1
0x0
0x1
0x2
0x3
0
1
0
1
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
Parity Enable
Disable parity generation and checking.
Enable parity generation and checking.
Parity Select.
Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
Forced "1" stick parity.
Forced "0" stick parity.
Break Control.
Disable break transmission.
Enable break transmission. Output pin UART TXD is forced to logic
0 when LCR[6] is active high.
Divisor Latch Access Bit.
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Reserved
Rev. 00.13 — 20 July 2011
Receiver Data Ready.
LSR[0] is set when the RBR holds an unread character and is
cleared when the UART RBR FIFO is empty.
RBR is empty.
RBR contains valid data.
Overrun Error.
The overrun error condition is set as soon as it occurs. A LSR
read clears LSR[1]. LSR[1] is set when UART RSR has a new
character assembled and the UART RBR FIFO is full. In this
case, the UART RBR FIFO will not be overwritten and the
character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
Chapter 32: LPC18xx USART0_2_3
…continued
UM10430
© NXP B.V. 2011. All rights reserved.
721 of 1164
Reset
Value
0
0
0
0
-
Reset
Value
0
0