LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 337

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
19.7.19 Dynamic Memory Configuration registers
Table 283. Static Memory Extended Wait register (STATICEXTENDEDWAIT - address
For example, for a static memory read/write transfer time of 16 µs, and a CCLK frequency
of 50 MHz, the following value must be programmed into this register:
(16 x 10
The DynamicConfig registers enable you to program the configuration information for the
relevant dynamic memory chip select. These registers are normally only modified during
system initialization. These registers are accessed with one wait state.
Table 284. Dynamic Memory Configuration registers (DYNAMICCONFIG, address
Bit
9:0
31:10 -
Bit
2:0
4:3
6:5
12:7
13
14
18:15 -
19
Symbol
EXTENDEDWAIT Extended wait time out.
Symbol
-
MD
-
AM0
-
AM1
B
-6
x 50 x 10
0x4000 5080) bit description
0x4000 5100 (DYNAMICCONFIG0), 0x4000 5120 (DYNAMICCONFIG1),
0x4000 5140 (DYNAMICCONFIG2), 0x4000 5160 (DYNAMICCONFIG3)) bit
description
All information provided in this document is subject to legal disclaimers.
Value Description
-
0x0
0x1
0x2
0x3
-
-
-
0
1
6
) / 16 - 1 = 49
Rev. 00.13 — 20 July 2011
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Memory device.
SDRAM (POR reset value).
Low-power SDRAM.
Reserved.
Reserved.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Address mapping.
See
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Address mapping
See
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Buffer enable.
Buffer disabled for accesses to this chip select (POR reset
value).
Buffer enabled for accesses to this chip select. After
configuration of the dynamic memory, the buffer must be
enabled for normal operation.
Description
16 clock cycles (POR reset value). The delay is in CCLK
cycles.
0x0 = 16 clock cycles.
0x1 - 0x3FF = (n+1) x16 clock cycles.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Table
Table
Chapter 19: LPC18xx External Memory Controller (EMC)
285. 000000 = reset value.
285. 0 = reset value.
[2]
[1]
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0x0
-
Reset
value
-
00
-
0
-
0
-