LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 302

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
18.6.3 Clock Divider Register (CLKDIV)
18.6.4 SD Clock Source Register (CLKSRC)
Table 227. Clock Divider Register (CLKDIV, address 0x4000 4008) bit description
Table 228. SD Clock Source Register (CLKSRC, address 0x4000 400C) bit description
Bit
7:0
15:8
23:16
31:24
Bit
31:0
Symbol
CLK_SOURCE Clock divider source for up to 16 SD cards supported. Each card
Symbol
CLK_DIVIDER0
CLK_DIVIDER1
CLK_DIVIDER2
CLK_DIVIDER3
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
has two bits assigned to it. For example, bits[1:0] assigned for
card-0, which maps and internally routes clock divider[3:0]
outputs to cclk_out[15:0] pins, depending on bit value.
00 - Clock divider 0
01 - Clock divider 1
10 - Clock divider 2
11 - Clock divider 3
In MMC-Ver3.3-only controller, only one clock divider supported.
The cclk_out is always from clock divider 0, and this register is
not implemented.
Description
Clock divider-0 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on.
Clock divider-1 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
mode, bits not implemented because only one clock divider
is supported.
Clock divider-2 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass),
value of 1 means divide by 2*1 = 2, value of ff means
divide by 2*255 = 510, and so on. In MMC-Ver3.3-only
mode, bits not implemented because only one clock divider
is supported.
Clock divider-3 value. Clock division is 2*n. For example,
value of 0 means divide by 2*0 = 0 (no division, bypass), a
value of 1 means divide by 2*1 = 2, a value of ff means
divide by 2*255 = 510, and so on.
In MMC-Ver3.3-only mode, bits not implemented because
only one clock divider is supported. divide by 2*0 = 0 (no
division, bypass), value of 1 means divide by 2*1 = 2, value
of ff means divide by 2*255 = 510, and so on. In
MMC-Ver3.3-only mode, bits not implemented because
only one clock divider is supported.
Chapter 18: LPC18xx SD/MMC interface
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
Reset
value
0