LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 520

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
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immediately polls the Transmit Descriptor list for the second frame. If the second frame is
valid, the transmit process transfers this frame before writing the first frame’s status
information.
In OSF mode, the Run state Transmit DMA operates in the following sequence:
Remark: As the DMA fetches the next descriptor in advance before closing the current
descriptor, the descriptor chain should have more than 2 different descriptors for correct
and proper operation.
The basic flow is described in
1. The DMA operates as described in steps 1 to 6 of the TxDMA (default mode).
2. Without closing the previous frame’s last descriptor, the DMA fetches the next
3. If the DMA owns the acquired descriptor, the DMA decodes the transmit buffer
4. The DMA fetches the Transmit frame from the Host memory and transfers the frame
5. The DMA waits for the previous frame’s frame transmission status and time stamp.
6. If enabled, the Transmit interrupt is set, the DMA fetches the next descriptor, then
7. In Suspend mode, if a pending status and time stamp are received from the MTL, the
8. The DMA can exit Suspend mode and enter the Run state (go to Step 1 or Step 2
descriptor.
address in this descriptor. If the DMA does not own the descriptor, the DMA goes into
Suspend mode and skips to Step 7.
to the MTL until the End-of-Frame data is transferred, closing the intermediate
descriptors if this frame is split across multiple descriptors.
Once the status is available, the DMA writes the time stamp to TDES2 and TDES3, if
such time stamp was captured (as indicated by a status bit). The DMA then writes the
status, with a cleared Own bit, to the corresponding TDES0, thus closing the
descriptor. If time stamping was not enabled for the previous frame, the DMA does not
alter the contents of TDES2 and TDES3.
proceeds to Step 3 (when Status is normal). If the previous transmission status shows
an underflow error, the DMA goes into Suspend mode (Step 7).
DMA writes the time stamp (if enabled for the current frame) to TDES2 and TDES3,
then writes the status to the corresponding TDES0. It then sets relevant interrupts and
returns to Suspend mode.
depending on pending status) only after receiving a Transmit Poll demand (DMA
Transmit Poll Demand register).
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Figure
48.
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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