LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 531

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 437. Transmit descriptor word 0 (TDES0)
Bit
15
16
17
19:18
20
21
23:22
24
25
Symbol
ES
IHE
TTSS
-
TCH
TER
CIC
-
TTSE
All information provided in this document is subject to legal disclaimers.
Description
Error Summary
Indicates the logical OR of the following bits:
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
• TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow Error
• TDES0[16]: IP Header Error
• TDES0[12]: IP Payload Error
IP Header Error
When set, this bit indicates that the MAC transmitter detected an error in the
IP datagram header. The transmitter checks the header length in the IPv4
packet against the number of header bytes received from the application and
indicates an error status if there is a mismatch. For IPv6 frames, a header
error is reported if the main header length is not 40 bytes. Furthermore, the
Ethernet Length/Type field value for an IPv4 or IPv6 frame must match the
IP header version received with the packet. For IPv4 frames, an error status
is also indicated if the Header Length field has a value less than 0x5.
Transmit Timestamp Status
This field is used as a status bit to indicate that a timestamp was captured for
the described transmit frame. When this bit is set, TDES2 and TDES3 have
a timestamp value captured for the transmit frame. This field is only valid
when the descriptor’s Last Segment control bit (TDES0[29]) is set.
Reserved
Second Address Chained
When set, this bit indicates that the second address in the descriptor is the
Next Descriptor address rather than the second buffer address. When
TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t care” value. TDES0[21]
takes precedence over TDES0[20].
Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor.
The DMA returns to the base address of the list, creating a descriptor ring.
Checksum Insertion Control
These bits control the checksum calculation and insertion. Bit encodings are
as shown below.
• 00: Checksum Insertion Disabled.
• 01: Only IP header checksum calculation and insertion are enabled.
• 10: IP header checksum and payload checksum calculation and insertion
are enabled, but pseudo-header checksum is not calculated in hardware.
• 11: IP Header checksum and payload checksum calculation and insertion
are enabled, and pseudo-header checksum is calculated in hardware.
This field is reserved when the IPC_FULL_OFFLOAD configuration
parameter is not selected.
Reserved
Transmit Timestamp Enable
When set, this bit enables IEEE1588 hardware time stamping for the
transmit frame referenced by the descriptor. This field is valid only when the
First Segment control bit (TDES0[28]) is set.
Rev. 00.13 — 20 July 2011
Chapter 22: LPC18xx Ethernet
UM10430
© NXP B.V. 2011. All rights reserved.
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