LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 252

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 170. Register overview: GPIO port (base address 0x400F 4000)
[1]
<Document ID>
User manual
Name
NOT2
NOT3
NOT4
NOT5
NOT6
NOT7
“ext” in this table and subsequent tables indicates that the data read after reset depends on the state of the pin, which in turn may
depend on an external source.
15.5.1.1 Pin interrupt mode register
15.5.1.2 Pin interrupt level (rising edge interrupt) enable register
15.5.1 GPIO pin interrupts register description
Access
WO
WO
WO
WO
WO
WO
For each of the 8 pin interrupts selected in
register determines whether the interrupt is edge or level sensitive.
Table 171. Pin interrupt mode register (ISEL, address 0x4008 7000) bit description
For each of the 8 pin interrupts selected in the PINTSEL registers (see
Table
interrupt mode configured in the ISEL register:
Table 172. Pin interrupt level (rising edge interrupt enable) register (IENR, address 0x4008
Bit
7:0
31:8
Bit
7:0
31:8
•
•
If the pin interrupt mode is edge sensitive (PMODE = 0), the rising edge interrupt is
enabled.
If the pin interrupt mode is level sensitive (PMODE = 1), the level interrupt is enabled.
The PINTEN_F register configures the active level (HIGH or LOW) for this interrupt.
131), one bit in the IENR register enables the interrupt depending on the pin
Address
offset
0x2308
0x230C
0x2310
0x2314
0x2318
0x231C
Symbol Description
PMODE Selects the interrupt mode for each pin interrupt. Bit n
-
Symbol Description
ENRL
-
7004) bit description
All information provided in this document is subject to legal disclaimers.
configures the pin interrupt selected in PINTSELn.
0 = Edge sensitive
1 = Level sensitive
Reserved.
Enables the rising edge or level interrupt for each pin
interrupt. Bit n configures the pin interrupt selected in
PINTSELn.
0 = Disable rising edge or level interrupt.
1 = Enable rising edge or level interrupt.
Reserved.
Rev. 00.13 — 20 July 2011
Description
Toggle port 2
Toggle port 3
Toggle port 4
Toggle port 5
Toggle port 6
Toggle port 7
Table 130
and
Table
Chapter 15: LPC18xx GPIO
Reset
value
NA
NA
NA
NA
NA
NA
131, one bit in the ISEL
UM10430
Width
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
word (32 bit)
© NXP B.V. 2011. All rights reserved.
Table 130
Reset
value
0
-
Reset
value
0
-
252 of 1164
Access
R/W
-
Access
R/W
-
and