LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 367

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 309. USB Status register in device mode (USBSTS_D - address 0x4000 6144) register bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
20.6.4.1 Device mode
Symbol
UI
UEI
PCI
-
-
AAI
URI
Value
0
1
0
1
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
USB interrupt
This bit is cleared by software writing a one to it.
This bit is set by the Host/Device Controller when
the cause of an interrupt is a completion of a USB
transaction where the Transfer Descriptor (TD)
has an interrupt on complete (IOC) bit set.
This bit is also set by the Host/Device Controller
when a short packet is detected. A short packet is
when the actual number of bytes received was
less than the expected number of bytes.
USB error interrupt
This bit is cleared by software writing a one to it.
When completion of a USB transaction results in
an error condition, this bit is set by the
Host/Device Controller. This bit is set along with
the USBINT bit, if the TD on which the error
interrupt occurred also had its interrupt on
complete (IOC) bit set. The device controller
detects resume signaling only (see
Section
Port change detect.
This bit is cleared by software writing a one to it.
The Device Controller sets this bit to a one when
the port controller enters the full or high-speed
operational state. When the port controller exits
the full or high-speed operation states due to
Reset or Suspend events, the notification
mechanisms are the USB Reset Received bit
(URI) and the DCSuspend bits (SLI) respectively.
Not used in Device mode.
Reserved.
Not used in Device mode.
USB reset received
This bit is cleared by software writing a one to it.
When the device controller detects a USB Reset
and enters the default state, this bit will be set to a
one.
Rev. 00.13 — 20 July 2011
20.10.11.6).
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Reset
value
0
0
0
0
0
0
UM10430
© NXP B.V. 2011. All rights reserved.
Access
R/WC
R/WC
R/WC
-
-
-
R/WC
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