LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 423

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
20.10.8.2 Data phase
20.10.8.3 Status phase
20.10.8.4 Control endpoint bus response matrix
Remark: After receiving a new setup packet the status and/or handshake phases may still
be pending from a previous control sequence. These should be flushed & deallocated
before linking a new status and/or handshake dTD for the most recent setup packet.
Following the setup phase, the DCD must create a device transfer descriptor for the data
phase and prime the transfer.
After priming the packet, the DCD must verify a new setup packet has not been received
by reading the ENDPTSETUPSTAT register immediately verifying that the prime had
completed. A prime will complete when the associated bit in the ENDPTPRIME register is
zero and the associated bit in the ENDPTSTATUS register is a one. If a prime fails, i.e.
The ENDPTPRIME bit goes to zero and the ENDPTSTATUS bit is not set, then the prime
has failed. This can only be due to improper setup of the dQH, dTD or a setup arriving
during the prime operation. If a new setup packet is indicated after the ENDPTPRIME bit
is cleared, then the transfer descriptor can be freed and the DCD must reinterpret the
setup packet.
Should a setup arrive after the data stage is primed, the device controller will
automatically clear the prime status (ENDPTSTATUS) to enforce data coherency with the
setup packet.
Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control
endpoints.
Remark: Error handling of data phase packets is the same as bulk packets described
previously.
Similar to the data phase, the DCD must create a transfer descriptor (with byte length
equal zero) and prime the endpoint for the status phase. The DCD must also perform the
same checks of the ENDPTSETUPSTAT as described above in the data phase.
Remark: The MULT field in the dQH must be set to “00” for bulk, interrupt, and control
endpoints.
Remark: Error handling of data phase packets is the same as bulk packets described
previously.
Shown in the following table is the device controller response to packets on a control
endpoint according to the device controller state.
•
•
f. Process setup packet using local software byte array copy and execute
g. Before priming for status/handshake phases ensure that ENDPTSETUPSTAT is
A poll loop should be used to wait until ENDPTSETUPSTAT transitions to ‘0’ after step
a) above and before priming for the status/handshake phases.
The time from writing a ‘1’ to ENDPTSETUPSTAT and reading back a ‘0’ is very short
(~1-2 us) so a poll loop in the DCD will not be harmful.
status/handshake phases.
‘0’.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
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