LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 440

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 361. Register overview: USB1 host/device controller (register base address 0x4000 7000)
<Document ID>
User manual
Name
TTCTRL
BURSTSIZE
TXFILLTUNING
-
ULPIVIEWPORT
BINTERVAL
ENDPTNAK
ENDPTNAKEN
CONFIGFLAG
PORTSC1_D
PORTSC1_H
-
-
USBMODE_D
USBMODE_H
Device endpoint registers
ENDPTSETUPSTAT
ENDPTPRIME
ENDPTFLUSH
ENDPTSTAT
ENDPTCOMPLETE
ENDPTCTRL0
ENDPTCTRL1
ENDPTCTRL2
ENDPTCTRL3
21.6.1 Device/host capability registers
Table 362. CAPLENGTH register (CAPLENGTH - address 0x4000 7100) bit description
Bit
7:0
23:8
31:24
R/W
R/W
R/W
R/W
Access Address
R/W
R/W
R/W
-
R/W
R/W
R/W
R/W
RO
-
-
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
Symbol
CAPLENGTH
HCIVERSION
-
offset
0x15C
0x160
0x164
0x168 -
0x16C
0x170
0x174
0x178
0x17C
0x180
0x184
0x184
0x188 -
0x1A0
0x1A4
0x1A8
0x1A8
0x1AC
0x1B0
0x1B4
0x1B8
0x1BC
0x1C0
0x1C4
0x1C8
0x1CC
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Description
Asynchronous buffer status for
embedded TT (host mode)
Programmable burst size
Host transmit pre-buffer packet tuning
(host mode)
Reserved
ULPI viewport
Length of virtual frame
Endpoint NAK (device mode)
Endpoint NAK Enable (device mode)
Configured flag register
Port 1 status/control (device mode)
Port 1 status/control (host mode)
-
-
USB mode (device mode)
USB mode (host mode)
Endpoint setup status
Endpoint initialization
Endpoint de-initialization
Endpoint status
Endpoint complete
Endpoint control 0
Endpoint control 1
Endpoint control 2
Endpoint control 3
Description
Indicates offset to add to the register base
address at the beginning of the Operational
Register
BCD encoding of the EHCI revision number
supported by this host controller.
These bits are reserved and should be set to
zero.
Chapter 21: LPC18xx USB1 Host/Device controller
Reset value
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
0x0000 0000
Reset value Access
0x40
0x100
-
UM10430
…continued
© NXP B.V. 2011. All rights reserved.
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RO
RO
-