LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1128

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 290. Static Memory Read Delay registers
Table 291. Static Memory Page Mode Read Delay registers
Table 292. Static Memory Write Delay registers
Table 293. Static Memory Turn Round Delay registers
Table 294. USB0 clocking and power control . . . . . . . . .354
Table 295. USB related acronyms . . . . . . . . . . . . . . . . . .355
Table 296. Fixed endpoint configuration . . . . . . . . . . . . .356
Table 297. USB Packet size . . . . . . . . . . . . . . . . . . . . . .357
Table 298. USB0 pin description . . . . . . . . . . . . . . . . . . .357
Table 299. Register access abbreviations . . . . . . . . . . . .358
Table 300. Register overview: USB0 OTG controller (register
Table 301. CAPLENGTH register (CAPLENGTH - address
Table 302. HCSPARAMS register (HCSPARAMS - address
Table 303. HCCPARAMS register (HCCPARAMS - address
Table 304. DCIVERSION register (DCIVERSION - address
Table 305. DCCPARAMS (address 0x4000 6124) . . . . .362
Table 306. USB Command register in device mode
Table 307. USB Command register in host mode
Table 308. Frame list size values . . . . . . . . . . . . . . . . . .366
Table 309. USB Status register in device mode (USBSTS_D
Table 310. USB Status register in host mode (USBSTS_H -
<Document ID>
User manual
(STATICWAITOEN0), 0x4000 5228
(STATICWAITOEN1), 0x4000 5248
(STATICWAITOEN2), 0x4000 5268
(STATICWAITOEN3)) bit description . . . . . . .343
(STATICWAITRD, address 0x4000 520C
(STATICWAITRD0), 0x4000 522C
(STATICWAITRD1), 0x4000 524C
(STATICWAITRD2), 0x4000 526C
(STATICWAITRD3)) bit description. . . . . . . . .343
(STATICWAITPAGE, address 0x4000 5210
(STATICWAITPAGE0), 0x4000 5230
(STATICWAITPAGE1), 0x4000 5250
(STATICWAITPAGE2), 0x4000 5270
(STATICWAITPAGE3)) bit description . . . . . .344
(STATICWAITWR, address 0x4000 5214
(STATICWAITWR0), 0x4000 5234
(STATICWAITWR1), 0x4000 5254
(STATICWAITWR2), 0x4000 5274
(STATICWAITWR3)) bit description . . . . . . . .344
(STATICWAITTURN, address 0x4000 5218
(STATICWAITTURN0), 0x4000 5238
(STATICWAITTURN1), 0x4000 5258
(STATICWAITTURN2), 0x4000 5278
(STATICWAITTURN3)) bit description . . . . . .345
base address 0x4000 6000) . . . . . . . . . . . . .358
0x4000 6100) bit description . . . . . . . . . . . . .360
0x4000 6104) bit description
0x4000 6108) bit description . . . . . . . . . . . . .361
0x4000 6120) bit description . . . . . . . . . . . . .362
(USBCMD_D - address 0x4000 6140) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .362
(USBCMD_H - address 0x4000 6140) bit
description - host mode . . . . . . . . . . . . . . . . .364
- address 0x4000 6144) register bit description .
367
address 0x4000 6144) register bit description . .
369
. . . . . . . . . . . .361
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 311. USB Interrupt register in device mode
Table 312. USB Interrupt register in host mode (USBINTR_H
Table 313. USB frame index register in device mode
Table 314. USB frame index register in host (FRINDEX_H -
Table 315. Number of bits used for the frame list index . 373
Table 316. USB Device Address register in device mode
Table 317. USB Periodic List Base register in host mode
Table 318. USB Endpoint List Address register in device
Table 319. USB Asynchronous List Address register in host
Table 320. USB TT Control register in host mode (TTCTRL -
Table 321. USB burst size register (BURSTSIZE - address
Table 322. USB Transfer buffer Fill Tuning register in host
Table 323. USB BINTERVAL register (BINTERVAL - address
Table 324. USB endpoint NAK register (ENDPTNAK -
Table 325. USB Endpoint NAK Enable register
Table 326. Port Status and Control register in device mode
Table 327. Port Status and Control register in host mode
Table 328. Port states as described by the PE and SUSP bits
Table 329. OTG Status and Control register (OTGSC -
Table 330. USB Mode register in device mode
Table 331. USB Mode register in host mode (USBMODE_H
Table 332. USB Endpoint Setup Status register
Table 333. USB Endpoint Prime register (ENDPTPRIME -
(USBINTR_D - address 0x4000 6148) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 371
- address 0x4000 6148) bit description . . . . 372
(FRINDEX_D - address 0x4000 614C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 373
address 0x4000 614C) bit description . . . . . 373
(DEVICEADDR - address 0x4000 6154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 374
(PERIODICLISTBASE - address 0x4000 6154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
mode (ENDPOINTLISTADDR - address 0x4000
6158) bit description . . . . . . . . . . . . . . . . . . . 375
mode (ASYNCLISTADDR- address 0x4000 6158)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 375
address 0x4000 615C) bit description . . . . . . 376
0x4000 6160) bit description - device/host mode
376
mode (TXFILLTUNING - address 0x4000 6164)
bit description . . . . . . . . . . . . . . . . . . . . . . . . 377
0x4000 6174) bit description . . . . . . . . . . . . . 378
address 0x4000 6178) bit description . . . . . . 378
(ENDPTNAKEN - address 0x4000 617C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 379
(PORTSC1_D - address 0x4000 6184) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 379
(PORTSC1_H - address 0x4000 6184) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
in the PORTSC1 register . . . . . . . . . . . . . . . . 386
address 0x4000 61A4) bit description . . . . . 387
(USBMODE_D - address 0x4000 61A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . 389
- address 0x4000 61A8) bit description . . . . 390
(ENDPTSETUPSTAT - address 0x4000 61AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
address 0x4000 61B0) bit description . . . . . 392
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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