LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 901

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 829. A/D Control register (CR - address 0x400E 3000 (ADC0) and 0x400E 4000 (ADC1)) bit description
<Document ID>
User manual
Bit
7:0
15:8
Symbol
SEL
CLKDIV
38.6.1 A/D Control register
Value
Table 828. Register overview: ADC1 (base address 0x400E 4000)
[1]
The A/D Control Register provides bits to select A/D channels to be converted, A/D timing,
A/D modes, and the A/D start trigger.
Name
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
STAT
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Description
Selects which of the ADC[7:0] pins are to be sampled and converted. Bit 0
selects Pin ADC0, bit 1 selects pin AD1,..., and bit 7 selects pin ADC7. In
software-controlled mode, only one of these bits should be 1. In hardware scan
mode, any value containing 1 to 8 ones. All zeroes is equivalent to 0x01.
The ADC clock is divided by the CLKDIV value plus one to produce the clock
for the A/D converter, which should be less than or equal to 4.5 MHz. Typically,
software should program the smallest value in this field that yields a clock of
4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog
source) a slower clock may be desirable.
Access Address
RO
RO
RO
RO
RO
RO
RO
RO
RO
All information provided in this document is subject to legal disclaimers.
offset
0x010
0x014
0x018
0x01C
0x020
0x024
0x028
0x02C
0x030
Rev. 00.13 — 20 July 2011
A/D Channel 0 Data Register. This register
A/D Channel 1 Data Register. This register
A/D Channel 2 Data Register. This register
A/D Channel 3 Data Register. This register
A/D Channel 4 Data Register. This register
A/D Channel 5 Data Register. This register
A/D Channel 6 Data Register. This register
A/D Channel 7 Data Register. This register
A/D Status Register. This register contains
Description
contains the result of the most recent
conversion completed on channel 0
contains the result of the most recent
conversion completed on channel 1.
contains the result of the most recent
conversion completed on channel 2.
contains the result of the most recent
conversion completed on channel 3.
contains the result of the most recent
conversion completed on channel 4.
contains the result of the most recent
conversion completed on channel 5.
contains the result of the most recent
conversion completed on channel 6.
contains the result of the most recent
conversion completed on channel 7.
DONE and OVERRUN flags for all of the A/D
channels, as well as the A/D interrupt flag.
Chapter 38: LPC18xx 10-bit ADC0/1
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
-
-
-
-
-
-
-
-
0
901 of 1164
[1]
Reset
value
0
0