LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 617

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.7.10.1.4 Configure multiple states
24.7.10.1.5 Miscellaneous options
24.7.10.2 Operate the SCT
1. In the EVSTATEMASK register for each event (up to 16 events, one register per
2. Determine how the event affects the system’s state:
1. Configure the SCT (see
2. Write to the STATE register to define the initial state. By default this is state 0.
3. To start the SCT, write to the CTRL register:
4. To stop the counters by software at any time, stop or halt the counter (write to
•
•
•
– Set the corresponding event bit in the DMAREQ0/1 registers for the event to
event), select the state or states (up to 31) this event is allowed to occur in. Each state
can be selected for more than one event.
In the EVCTRL registers (up to 16 events, one register per event), set the new state
value in the STATEV field for this event. If the event is the highest numbered in the
current state, this value is either added to the existing state value or replaces the
existing state value, depending on the field STATELD.
Remark: If there are higher numbered events in the current state, the state cannot be
changed by this event.
If the STATEV and STATELD values are set to zero, the state does not change.
There are a certain (selectable) number of capture registers. Each capture register
can be programmed to capture the counter contents when one or more events occur.
If the counter is in bidirectional mode, the effect of set and clear of an output can be
made to depend on whether the counter is counting up or down by writing to the
OUTPUTDIRCTRL register.
a. Configure the counter (see
b. Configure the match and capture registers (see
c. Configure the events and event responses (see
d. Configure multiple states
– Clear the counters.
– Clear or set the STOP_L and/or STOP_H bits.
– For each counter select unidirectional or bidirectional counting mode (field
– Select the prescale factor for the counter clock (CTRL register).
– Clear the HALT_L and/or HALT_H bit. By default, the counters are halted and no
STOP_L and/or STOP_H bits or HALT_L and/or HALT_H bits in the CTRL register).
trigger DMA requests 0 or 1.
Remark: The counter starts counting once the STOP bit is cleared as well. If the
STOP bit is set, the SCT will wait instead for an event to occur that is configured to
start the counter.
BIDIR_L and/or BIDIR_H).
events can occur.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Section 24.7.10.1 “Configure the
(Section
Chapter 24: LPC18xx State Configurable Timer (SCT)
Section
24.7.10.1.4).
24.7.10.1.1).
Section
Section
SCT”).
24.7.10.1.2).
24.7.10.1.3).
UM10430
© NXP B.V. 2011. All rights reserved.
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