LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1151

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
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Chapter 19: LPC18xx External Memory Controller (EMC)
19.1
19.2
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19.4
19.5
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19.7
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19.7.16
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
20.1
<Document ID>
User manual
How to read this chapter . . . . . . . . . . . . . . . . 322
Basic configuration . . . . . . . . . . . . . . . . . . . . 322
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
General description . . . . . . . . . . . . . . . . . . . . 323
Memory bank select . . . . . . . . . . . . . . . . . . . 324
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 325
Register description . . . . . . . . . . . . . . . . . . . 325
How to read this chapter . . . . . . . . . . . . . . . . 354
Command Register (CMD) . . . . . . . . . . . . . . 306
Response Register 0 (RESP0) . . . . . . . . . . . 309
Response Register 1 (RESP1) . . . . . . . . . . . 309
Response Register 2 (RESP2) . . . . . . . . . . . 309
Response Register 3 (RESP3) . . . . . . . . . . . 309
Masked Interrupt Status Register (MINTSTS) 309
Raw Interrupt Status Register (RINTSTS) . . 310
Status Register (STATUS) . . . . . . . . . . . . . . 312
FIFO Threshold Watermark Register (FIFOTH) . .
313
Card Detect Register (CDETECT) . . . . . . . . 315
Write Protect Register (WRTPRT) . . . . . . . . 315
General Purpose Input/Output Register (GPIO) . .
315
Transferred CIU Card Byte Count Register
(TCBCNT). . . . . . . . . . . . . . . . . . . . . . . . . . . 315
Transferred Host to BIU-FIFO Byte Count
Register (TBBCNT). . . . . . . . . . . . . . . . . . . . 316
EMC Control register . . . . . . . . . . . . . . . . . . 327
EMC Status register . . . . . . . . . . . . . . . . . . . 328
EMC Configuration register . . . . . . . . . . . . . 329
Dynamic Memory Control register . . . . . . . . 329
Dynamic Memory Refresh Timer register . . . 331
Dynamic Memory Read Configuration register . .
331
Dynamic Memory Precharge Command Period
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
Dynamic Memory Active to Precharge Command
Period register . . . . . . . . . . . . . . . . . . . . . . . 332
Dynamic Memory Self Refresh Exit Time register
333
Dynamic Memory Last Data Out to Active Time
register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333
Dynamic Memory Data In to Active Command
Time register . . . . . . . . . . . . . . . . . . . . . . . . 334
Dynamic Memory Write Recovery Time register .
334
Dynamic Memory Active to Active Command
Period register . . . . . . . . . . . . . . . . . . . . . . . 334
Dynamic Memory Auto-refresh Period register . .
335
Dynamic Memory Exit Self Refresh register 335
Dynamic Memory Active Bank A to Active Bank B
Time register . . . . . . . . . . . . . . . . . . . . . . . . 336
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
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20.2
Functional description . . . . . . . . . . . . . . . . . 346
Low-power operation . . . . . . . . . . . . . . . . . . 348
External static memory interface. . . . . . . . . 350
Basic configuration. . . . . . . . . . . . . . . . . . . . 354
Debounce Count Register (DEBNCE) . . . . . 316
User ID Register (USRID) . . . . . . . . . . . . . . 316
Version ID Register (VERID) . . . . . . . . . . . . 316
UHS-1 Register (UHS_REG) . . . . . . . . . . . . 317
Hardware Reset (RST_N) . . . . . . . . . . . . . . 317
Bus Mode Register (BMOD) . . . . . . . . . . . . 317
Poll Demand Register (PLDMND) . . . . . . . . 318
Descriptor List Base Address Register (DBADDR)
318
Internal DMAC Status Register (IDSTS) . . . 319
Internal DMAC Interrupt Enable Register
(IDINTEN) . . . . . . . . . . . . . . . . . . . . . . . . . . 320
Current Host Descriptor Address Register
(DSCADDR). . . . . . . . . . . . . . . . . . . . . . . . . 320
Current Buffer Descriptor Address Register
(BUFADDR) . . . . . . . . . . . . . . . . . . . . . . . . . 321
Dynamic Memory Load Mode register to Active
Command Time . . . . . . . . . . . . . . . . . . . . . . 336
Static Memory Extended Wait register . . . . 336
Dynamic Memory Configuration registers . . 337
Dynamic Memory RAS & CAS Delay registers . .
340
Static Memory Configuration registers . . . . . 340
Static Memory Write Enable Delay registers 342
Static Memory Output Enable Delay registers . .
343
Static Memory Read Delay registers . . . . . . 343
Static Memory Page Mode Read Delay registers
343
Static Memory Write Delay registers . . . . . . 344
Static Memory Turn Round Delay registers
AHB slave register interface . . . . . . . . . . . . 346
AHB slave memory interface . . . . . . . . . . . . 347
Memory transaction endianness . . . . . . . . . 347
Memory transaction size . . . . . . . . . . . . . . . 347
Write protected memory areas. . . . . . . . . . . 347
Pad interface . . . . . . . . . . . . . . . . . . . . . . . . 347
Data buffers . . . . . . . . . . . . . . . . . . . . . . . . . 347
Write buffers. . . . . . . . . . . . . . . . . . . . . . . . . 347
Read buffers . . . . . . . . . . . . . . . . . . . . . . . . 348
Low-power SDRAM Deep-sleep Mode . . . . 349
Low-power SDRAM partial array refresh . . . 349
32-bit wide memory bank connection . . . . . 350
16-bit wide memory bank connection . . . . . 351
8-bit wide memory bank connection . . . . . . 352
Memory configuration example . . . . . . . . . . 353
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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