LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1067

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 994. I2S Digital Audio Output register (DAO - address 0x400A 2000) bit description
Table 995. I2S Digital Audio Input register (DAI - address 0x400A 2004) bit description
<Document ID>
User manual
Bit
1:0
2
3
4
5
14:6
15
31:16 -
Bit
1:0
2
3
4
5
14:6
31:15 -
MUTE
Symbol
WORDWIDTH
MONO
STOP
RESET
WS_SEL
WS_HALFPERIOD
Symbol
WORDWIDTH
MONO
STOP
RESET
WS_SEL
WS_HALFPERIOD
42.9.6.2 I2S Digital Audio Input register
42.9.6.3 I2S Transmit FIFO register
The DAI register controls the operation of the I2S receive channel. The function of bits in
DAI are shown in
The TXFIFO register provides access to the transmit FIFO. The function of bits in TXFIFO
are shown in
Value Description
0x0
0x1
0x2
0x3
Value Description
0x0
0x1
0x2
0x3
When 0, the interface is in master mode. When 1, the interface is in slave
Selects the number of bytes in data as follows:
8-bit data
16-bit data
Reserved, do not use this setting
32-bit data
When 1, data is of monaural format. When 0, the data is in stereo format.
When 1, disables accesses on FIFOs, places the transmit channel in mute
mode.
When 1, asynchronously resets the transmit channel and FIFO.
mode. See
with TXMODE.
Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
When 1, the transmit channel sends only zeroes.
Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Selects the number of bytes in data as follows:
8-bit data
16-bit data
Reserved, do not use this setting
32-bit data
When 1, data is of monaural format. When 0, the data is in stereo format.
When 1, disables accesses on FIFOs, places the transmit channel in mute
mode.
When 1, asynchronously reset the transmit channel and FIFO.
When 0, the interface is in master mode. When 1, the interface is in slave
mode. See
with RXMODE.
Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31. 0x1F
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
Table
All information provided in this document is subject to legal disclaimers.
Table
996.
Section 42.9.7.2
Rev. 00.13 — 20 July 2011
Section 42.9.7.2
995.
for a summary of useful combinations for this bit
for a summary of useful combinations for this bit
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
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0
0
0x1F
1
Reset
value
01
0
1
-
Reset
value
01
0
0
0
1
-