LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1142

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 1028. CAN message interface command mask 1
Table 1029. CAN message interface command mask 2
Table 1030. CAN message interface command arbitration 1
Table 1031. CAN message interface command arbitration 2
Table 1032. CAN message interface message control
Table 1033. CAN message interface data A1 registers
Table 1034. CAN message interface data A2 registers
Table 1035. CAN message interface data B1 registers
Table 1036. CAN message interface data B2 registers
Table 1037. CAN transmission request 1 register (TXREQ1,
Table 1038. CAN transmission request 2 register (TXREQ2,
Table 1039. CAN new data 1 register (ND1, address
Table 1040. CAN new data 2 register (ND2, address
Table 1041. CAN interrupt pending 1 register (IR1, address
Table 1042. CAN interrupt pending 2 register (IR2,
Table 1043. CAN message valid 1 register (MSGV1,
Table 1044. CAN message valid 2 register (MSGV2, address
Table 1045. CAN clock divider register (CLKDIV, address
Table 1046. Initialization of a transmit object. . . . . . . . . 1110
Table 1047. Initialization of a receive object . . . . . . . . . 1111
Table 1048. Parameters of the C_CAN bit time. . . . . . . 1116
Table 1049. Abbreviations . . . . . . . . . . . . . . . . . . . . . . 1119
<Document ID>
User manual
0x400E 2084) bit description . . . . . . . . . . . .1093
registers (IF1_MSK1, address 0x400E 2028 and
IF2_MSK1, address 0x400E 2088) bit description
1095
registers (IF1_MSK2, address 0x400E 202C and
IF2_MSK2, 0x400E 208C) bit description
registers (IF1_ARB1, address 0x400E 2030 and
IF2_ARB1, address 0x400E 2090) bit description
1095
registers (IF1_ARB2, address 0x400E 2034 and
IF2_ARB2, address 0x400E 2094) bit description
1096
registers (IF1_MCTRL, address 0x400E 2038 and
IF2_MCTRL, address 0x400E 2098) bit
description . . . . . . . . . . . . . . . . . . . . . . . . .1097
(IF1_DA1, address 0x400E 203C and IF2_DA1,
address 0x400E 209C) bit description . . . . .1098
(IF1_DA2, address 0x400E 2040 and IF2_DA2,
address 0x400E 20A0) bit description . . . . .1099
(IF1_DB1, address 0x400E 2044 and IF2_DB1,
address 0x400E 20A4) bit description . . . . .1099
(IF1_DB2, address 0x400E 2048 and IF2_DB2,
address 0x400E 20A8) bit description . . . . .1099
address 0x400E 2100) bit description . . . . .1099
address 0x400E 2104) bit description . . . . . 1100
0x400E 2120) bit description . . . . . . . . . . . . 1100
0x400E 2124) bit description . . . . . . . . . . . . 1101
0x400E 2140) bit description . . . . . . . . . . . . 1101
addresses 0x400E 2144) bit description . . . 1101
addresses 0x400E 2160) bit description . . . 1102
0x400E 2164) bit description . . . . . . . . . . . . 1102
0x400E 2180) bit description . . . . . . . . . . . . 1103
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1095
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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