LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 371

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 311. USB Interrupt register in device mode (USBINTR_D - address 0x4000 6148) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
15:9
16
17
18
19
31:20 -
Symbol Description
UE
UEE
PCE
-
-
-
URE
SRE
SLE
-
NAKE
-
-
-
20.6.5.1 Device mode
20.6.5 USB Interrupt register (USBINTR)
USB interrupt enable
When this bit is one, and the USBINT bit in the USBSTS register is one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBINT bit in USBSTS.
USB error interrupt enable
When this bit is a one, and the USBERRINT bit in the USBSTS register is a one, the
host/device controller will issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software clearing the USBERRINT bit in the USBSTS
register.
Port change detect enable
When this bit is a one, and the Port Change Detect bit in the USBSTS register is a
one, the host/device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the Port Change Detect bit in USBSTS.
Not used by the Device controller.
Reserved
Not used by the Device controller.
USB reset enable
When this bit is a one, and the USB Reset Received bit in the USBSTS register is a
one, the device controller will issue an interrupt. The interrupt is acknowledged by
software clearing the USB Reset Received bit.
SOF received enable
When this bit is a one, and the SOF Received bit in the USBSTS register is a one, the
device controller will issue an interrupt. The interrupt is acknowledged by software
clearing the SOF Received bit.
Sleep enable
When this bit is a one, and the DCSuspend bit in the USBSTS
register transitions, the device controller will issue an interrupt. The interrupt is
acknowledged by software writing a one to the DCSuspend bit.
Reserved
NAK interrupt enable
This bit is set by software if it wants to enable the hardware interrupt for the NAK
Interrupt bit. If both this bit and the corresponding NAK Interrupt bit are set, a
hardware interrupt is generated.
Reserved
Not used by the Device controller.
Not used by the Device controller.
Reserved
The software interrupts are enabled with this register. An interrupt is generated when a bit
is set and the corresponding interrupt is active. The USB Status register (USBSTS) still
shows interrupt sources even if they are disabled by the USBINTR register, allowing
polling of interrupt events by the software. All interrupts must be acknowledged by
software by clearing (that is writing a 1 to) the corresponding bit in the USBSTS register.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
0
0
0
-
0
371 of 1164
Access
R/W
R/W
R/W
-
R/W
R/W
R/W
-
R/W