LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 610

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 524. SCT event control register 0 to 15 (EVCTRL - address 0x4000 0304 (EVCTRL0) to 0x4000 037C
<Document ID>
User manual
Bit
14
19:15 STATEV
31:20 -
Symbol
STATELD
(EVCTRL15)) bit description
24.6.25 SCT output set registers 0 to 15
24.6.26 SCT output clear registers 0 to 15
Value Description
0
1
Each output n has one set register that controls how events effect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
SCTOUTPUTDIRCTRL register.
Table 525. SCT output set register 0 to 15 (OUTPUTSET - address 0x4000 0500
Each output n has one clear register that controls how events effect each output. Whether
outputs are set or cleared depends on the setting of the SETCLRn field in the
OUTPUTDIRCTRL register.
Table 526. SCT output set register 0 to 15 (OUTPUTCL - address 0x4000 0504 (OUTPUTCL0)
Bit
15:0
31:16
Bit
15:0
31:16
This bit controls how the STATEV value modifies the state selected by HEVENT when
this event is the highest-numbered event occurring for that state.
STATEV value is added into STATE (the carry-out is ignored).
STATEV value is loaded into STATE.
This value is loaded into or added to the state selected by HEVENT, depending on
STATELD, when this event is the highest-numbered event occurring for that state. If
STATELD and STATEV are both zero, there is no change to the STATE value.
Reserved
Symbol
SET
-
Symbol
CLR
-
(OUTPUTSET0) to 0x4000 0578 (OUTPUTSET15)) bit description
to 0x4000 057C (OUTPUTCL15)) bit description
All information provided in this document is subject to legal disclaimers.
Description
A 1 in bit m selects event m to set output n (or clear it if SETCLRn =
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
Reserved
Description
A 1 in bit m selects event m to clear output n (or set it if SETCLRn =
0x1 or 0x2) event 0 = bit 0, event 1 = bit 1,..., event 15 = bit 15.
Reserved
Rev. 00.13 — 20 July 2011
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
Reset
value
0
Reset
value