LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 393

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 334. USB Endpoint Flush register (ENDPTFLUSH - address 0x4000 61B4) bit description
Table 335. USB Endpoint Status register (ENDPTSTAT - address 0x4000 61B8) bit description
<Document ID>
User manual
Bit
15:6
21:16 FETB
31:22 -
Bit
5:0
15:6
21:16 ETBR
31:22 -
Symbol
-
Symbol
ERBR
-
20.6.21 USB Endpoint Status register (ENDPTSTAT)
20.6.22 USB Endpoint Complete register (ENDPTCOMPLETE)
Description
reserved
Flush endpoint transmit buffer for physical IN endpoints 5 to 0.
Writing a one to a bit(s) will clear any primed buffers.
FETB0 = endpoint 0
...
FETB5 = endpoint 5
reserved
Description
Endpoint receive buffer ready for physical OUT endpoints 5 to 0.
This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ERBR0 = endpoint 0
...
ERBR5 = endpoint 5
reserved
Endpoint transmit buffer ready for physical IN endpoints 3 to 0.
This bit is set to 1 by hardware as a response to receiving a command from a
corresponding bit in the ENDPTPRIME register.
ETBR0 = endpoint 0
...
ETBR5 = endpoint 5
reserved
One bit for each endpoint indicates status of the respective endpoint buffer. This bit is set
by hardware as a response to receiving a command from a corresponding bit in the
ENDPTPRIME register. There will always be a delay between setting a bit in the
ENDPTPRIME register and endpoint indicating ready. This delay time varies based upon
the current USB traffic and the number of bits set in the ENDPTPRIME register. Buffer
ready is cleared by USB reset, by the USB DMA system, or through the ENDPTFLUSH
register.
Remark: These bits will be momentarily cleared by hardware during hardware endpoint
re-priming operations when a dTD is retired and the dQH is updated.
Each bit in this register indicates that a received/transmit event occurred and software
should read the corresponding endpoint queue to determine the transfer status. If the
corresponding IOC bit is set in the Transfer Descriptor, then this bit will be set
simultaneously with the USBINT.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 20: LPC18xx USB0 Host/Device/OTG controller
Reset
value
0
-
0
-
Reset
value
-
0
-
UM10430
© NXP B.V. 2011. All rights reserved.
Access
RO
-
RO
-
Access
-
R/WS
-
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