LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 845

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
36.7.3.4.1 Reception of a data frame
36.7.3.4.2 Reception of a remote frame
36.7.3.5 Receive/transmit priority
36.7.3.6 Configuration of a transmit object
If a match occurs, the scanning is stopped and the Message Handler state machine
proceeds depending on the type of frame (Data Frame or Remote Frame) received.
The Message Handler state machine stores the message from the CAN Core shift register
into the respective Message Object in the Message RAM. The data bytes, all arbitration
bits, and the Data Length Code are stored into the corresponding Message Object. This is
implemented to keep the data bytes connected with the identifier even if arbitration mask
registers are used.
The NEWDAT bit is set to indicate that new data (not yet seen by the CPU) has been
received. The CPU/software should reset NEWDAT when it reads the Message Object. If
at the time of the reception the NEWDAT bit was already set, MSGLST is set to indicate
that the previous data (supposedly not seen by the CPU) is lost. If the RxIE bit is set, the
INTPND bit is also set, causing the Interrupt Register to point to this Message Object.
The TXRQST bit of this Message Object is reset to prevent the transmission of a Remote
Frame, while the requested Data Frame has just been received.
When a Remote Frame is received, three different configurations of the matching
Message Object have to be considered:
The receive/transmit priority for the Message Objects is attached to the message number.
Message Object 1 has the highest priority, while Message Object 32 has the lowest
priority. If more than one transmission request is pending, they are serviced due to the
priority of the corresponding Message Object.
Table 795
Table
1. DIR = ‘1’ (direction = transmit), RMTEN = ‘1’, UMASK = ‘1’ or ’0’
2. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’0’
3. DIR = ‘1’ (direction = transmit), RMTEN = ‘0’, UMASK = ’1’
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object is set. The rest of the Message Object remains unchanged.
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object remains unchanged; the Remote Frame is ignored.
On the reception of a matching Remote Frame, the TXRQST bit of this Message
Object is reset. The arbitration and control field (Identifier + IDE + RTR + DLC) from
the shift register is stored into the Message Object in the Message RAM, and the
NEWDAT bit of this Message Object is set. The data field of the Message Object
remains unchanged; the Remote Frame is treated similar to a received Data Frame.
761):
shows how a transmit object should be initialized by software (see also
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 36: LPC18xx C_CAN
UM10430
© NXP B.V. 2011. All rights reserved.
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