LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 185

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

13.1 How to read this chapter
13.2 Basic configuration
13.3 General description
<Document ID>
User manual
13.3.1 Digital pin function
13.3.2 Digital pin mode
Remark: This chapter describes parts LPC1850/30/20/10 Rev ‘A’ and parts LPC18xx
(with on-chip flash). For a description of the SCU for parts LPC1850/30/20/10 Rev ‘-’, see
Section
The following peripherals are not available on all parts, and the corresponding bit values
that select those functions in the SFSP registers are reserved:
The SCU is configured as follows:
Table 108. SCU clocking and power control
The system control unit determines the function and electrical mode of the digital pins. By
default function 0 is selected for all pins with pull-up enabled.
Remark: Analog I/Os for the ADCs and the DAC as well as several USB functions reside
on separate pins and are not controlled through the SCU.
The FUNC bits in the SFSX_Y registers control the function of each pin. If the function is
GPIO, the GPIOnDIR registers determine whether the pin is configured as an input or
output (see
automatically depending on the pin’s functionality. The GPIOnDIR registers have no effect
for peripheral functions.
The MODE bits in the SFSX_Y registers allow the selection of on-chip pull-up or pull-down
resistors for each pin or select the repeater mode.
Clock to SCU register interface
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UM10430
Chapter 13: LPC18xx System Control Unit (SCU)
Rev. 00.13 — 20 July 2011
Ethernet: available on LPC1850/30.
USB0: available on LPC1850/30/20.
USB1: available on LPC1850/30.
See
The SCU is reset by the SCU_RST (reset # 9).
42.7.
Table 108
Table
All information provided in this document is subject to legal disclaimers.
280). For any peripheral function, the pin direction is controlled
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_M3_CLK
Branch clock
CLK_M3_SCU
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
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