LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 450

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 371. USB Status register in host mode (USBSTS_H - address 0x4000 7144) register bit description
<Document ID>
User manual
Bit
12
13
14
15
16
17
18
19
31:20
Symbol Value
HCH
RCL
PS
AS
-
-
UAI
UPI
-
0
1
0
1
0
1
0
1
0
1
0
1
Description
HCHalted
The RS bit in USBCMD is set to zero. Set by the host controller.
The Host Controller sets this bit to one after it has stopped executing
because of the Run/Stop bit being set to 0, either by software or by the
Host Controller hardware (e.g. because of an internal error).
Reclamation
No empty asynchronous schedule detected.
An empty asynchronous schedule is detected. Set by the host controller.
Periodic schedule status
This bit reports the current real status of the Periodic Schedule. The Host
Controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit in the
USBCMD register. When this bit and the Periodic Schedule Enable bit are
the same value, the Periodic Schedule is either enabled (if both are 1) or
disabled (if both are 0).
The periodic schedule status is disabled.
The periodic schedule status is enabled.
Asynchronous schedule status
This bit reports the current real status of the Asynchronous Schedule. The
Host Controller is not required to immediately disable or enable the
Asynchronous Schedule when software transitions the Asynchronous
Schedule Enable bit in the USBCMD register. When this bit and the
Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (if both are 1) or disabled (if both are 0).
Asynchronous schedule status is disabled.
Asynchronous schedule status is enabled.
Not used on Host mode.
Reserved.
USB host asynchronous interrupt (USBHSTASYNCINT)
This bit is cleared by software writing a one to it.
This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set and the TD was from the asynchronous
schedule. This bit is also set by the Host when a short packet is detected
and the packet is on the asynchronous schedule. A short packet is when
the actual number of bytes received was less than the expected number of
bytes.
USB host periodic interrupt (USBHSTPERINT)
This bit is cleared by software writing a one to it.
This bit is set by the Host Controller when the cause of an interrupt is a
completion of a USB transaction where the Transfer Descriptor (TD) has an
interrupt on complete (IOC) bit set and the TD was from the periodic
schedule. This bit is also set by the Host Controller when a short packet is
detected and the packet is on the periodic schedule. A short packet is
when the actual number of bytes received was less than the expected
number of bytes.
Reserved.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 21: LPC18xx USB1 Host/Device controller
UM10430
© NXP B.V. 2011. All rights reserved.
Reset
value
1
0
0
0
0
0
-
0
Access
RO
RO
RO
-
R/WC
-
R/WC
…continued
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