LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 862

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
37.7.7 I
SIC is the I
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the CONSET
register. Writing 0 has no effect.
I 2ENC is the I
CONSET register. Writing 0 has no effect.
This register controls the Monitor mode which allows the I
the I
Table 810. I
Bit
0
1
2
31:3 -
2
C Monitor mode control register
2
C bus without actually participating in traffic or interfering with the I
Symbol
MM_ENA
ENA_SCL
MATCH_ALL
0x400E 001C (I2C1)) bit description
2
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the CONSET
C Monitor mode control register (MMCTRL - address 0x400A 101C (I2C0) and
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
-
Rev. 00.13 — 20 July 2011
Monitor mode enable.
Monitor mode disabled.
The I
SDA output will be forced high. This will prevent the I
module from outputting data of any kind (including ACK)
onto the I
Depending on the state of the ENA_SCL bit, the output may
be also forced high, preventing the module from having
control over the I
SCL output enable.
When this bit is cleared to ‘0’, the SCL output will be forced
high when the module is in monitor mode. As described
above, this will prevent the module from having any control
over the I
When this bit is set, the I
control over the clock line that it would in normal operation.
This means that, acting as a slave peripheral, the I
module can “stretch” the clock line (hold it low) until it has
had time to respond to an I
Select interrupt register match.
When this bit is cleared, an interrupt will only be generated
when a match occurs to one of the (up-to) four address
registers described above. That is, the module will
respond as a normal slave as far as address-recognition is
concerned.
When this bit is set to ‘1’ and the I2C is in monitor mode, an
interrupt will be generated on ANY address received. This
will enable the part to monitor all traffic on the bus.
Reserved. The value read from reserved bits is not defined. -
2
C module will enter monitor mode. In this mode the
2
2
C data bus.
C clock line.
2
C clock line.
Chapter 37: LPC18xx I2C-bus interface
2
C module may exercise the same
2
C interrupt.
2
C module to monitor traffic on
[1]
UM10430
© NXP B.V. 2011. All rights reserved.
2
2
C bus.
C
2
C
862 of 1164
Reset
value
0
0
0