LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1054

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
42.8 LPC1850/30/20/10 Rev ‘-’ GPIO
<Document ID>
User manual
42.8.1 Basic configuration
42.8.2 Features
42.8.3 Pin description
42.8.4 Register description
The GPIO is configured as follows:
Table 978. GPIO clocking and power control
Table 979. GPIO pin description
Remark: The GPIO pins are typically shared with functions of other peripherals.
The LPC18xx has up to four 32-bit General Purpose I/O ports. For each GPIO port, the
first 16 pins are available with the exception of port 4 which does not use GPIO4_11.
The registers are located on the AHB for the fastest possible read and write timing. They
can also be accessed as byte or half-word long data. A mask register allows access to a
group of bits in a single GPIO port independently from other bits in the same port.
GPIO
Pin name
GPIO0_[15:0]
GPIO1_[15:0]
GPIO2_[15:0]
GPIO3_[15:0]
GPIO4_[15:0]
•
•
•
•
•
•
See
The GPIO is reset by a GPIO_RST (reset #28).
All GPIO pins are set to input by default.
Accelerated GPIO functions:
– GPIO registers are located on the AHB so that the fastest possible I/O timing can
– Mask registers allow treating sets of port bits as a group, leaving other bits
– All GPIO registers are byte and half-word addressable.
– Entire port value can be written in one instruction.
Bit-level set and clear registers allow a single instruction set or clear of any number of
bits in one port.
Direction control of individual bits.
be achieved.
unchanged.
Table 978
All information provided in this document is subject to legal disclaimers.
Type
I/O
I/O
I/O
I/O
I/O
for clocking and power control.
Base clock
BASE_M3_CLK
Rev. 00.13 — 20 July 2011
Description
GPIO port 0, I/Os 15 to 0.
GPIO port 1, I/Os 15 to 0.
GPIO port 2, I/Os 15 to 0.
GPIO port 3, I/Os 15 to 0.
GPIO port 4, I/Os 15 to 0. GPIO4_11 is not used out.
Branch clock
CLK_M3_GPIO
Chapter 42: Appendix
UM10430
© NXP B.V. 2011. All rights reserved.
Maximum
frequency
150 MHz
1054 of 1164