LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 1131

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 444. Receive descriptor fields 1 (RDES1) . . . . . . .537
Table 445. Receive descriptor fields 2 (RDES2) . . . . . . .537
Table 446. Receive descriptor fields 3 (RDES3) . . . . . . .538
Table 447. Receive descriptor fields 4 (RDES4) . . . . . . .538
Table 448. Receive descriptor fields 6 (RDES6) . . . . . . .539
Table 449. Receive descriptor fields 7 (RDES7) . . . . . . .539
Table 450. LCD clocking and power control . . . . . . . . . .540
Table 451. LCD controller pins . . . . . . . . . . . . . . . . . . . .543
Table 452. Pins used for single panel STN displays . . . .543
Table 453. Pins used for dual panel STN displays . . . . .544
Table 454. Pins used for TFT displays . . . . . . . . . . . . . .544
Table 455. Register overview: LCD controller (base address:
Table 456. Horizontal Timing register (TIMH, address
Table 457. Vertical Timing register (TIMV, address 0x4000
Table 458. Clock and Signal Polarity register (POL, address
Table 459. Line End Control register (LE, address 0x4000
Table 460. Upper Panel Frame Base register (UPBASE,
Table 461. Lower Panel Frame Base register (LPBASE,
Table 462. LCD Control register (CTRL, address 0x4000
Table 463. Interrupt Mask register (INTMSK, address
Table 464. Raw Interrupt Status register (INTRAW, address
Table 465. Masked Interrupt Status register (INTSTAT,
Table 466. Interrupt Clear register (INTCLR, address
Table 467. Upper Panel Current Address register (UPCURR,
Table 468. Lower Panel Current Address register (LPCURR,
Table 469. Color Palette registers (PAL, address 0x4000
Table 470. Cursor Image registers (CRSR_IMG, address
Table 471. Cursor Control register (CRSR_CTRL, address
Table 472. Cursor Configuration register (CRSR_CFG,
Table 473. Cursor Palette register 0 (CRSR_PAL0, address
Table 474. Cursor Palette register 1 (CRSR_PAL1, address
Table 475. Cursor XY Position register (CRSR_XY, address
Table 476. Cursor Clip Position register (CRSR_CLIP,
Table 477. Cursor Interrupt Mask register (CRSR_INTMSK,
<Document ID>
User manual
0x4000 8000) . . . . . . . . . . . . . . . . . . . . . . . . .545
0x4000 8000) bit description . . . . . . . . . . . . .546
8004) bit description . . . . . . . . . . . . . . . . . . .548
0x4000 8008) bit description
800C) bit description. . . . . . . . . . . . . . . . . . . .551
address 0x4000 8010) bit description. . . . . .551
address 0x4000 8014) bit description. . . . . .552
8018) bit description . . . . . . . . . . . . . . . . . . .552
0x4000 801C) bit description . . . . . . . . . . . . .554
0x4000 8020) bit description . . . . . . . . . . . . .554
address 0x4000 8024) bit description. . . . . .555
0x4000 8028) bit description . . . . . . . . . . . . .556
address 0x4000 802C) bit description . . . . .556
address 0x4000 8030) bit description. . . . . .556
8200 (PAL0) to 0x4000 83FC (PAL255)) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .557
0x4000 8800 (CRSR_IMG0) to 0x4000 8BFC
(CRSR_IMG1)) bit description . . . . . . . . . . . .558
0x4000 8C00) bit description . . . . . . . . . . . . .558
address 0x4000 8C04) bit description . . . . .559
0x4000 8C08) bit description . . . . . . . . . . . . .559
0x4000 8C0C) bit description . . . . . . . . . . . . .560
0x4000 8C10) bit description . . . . . . . . . . . . .560
address 0x4000 8C14) bit description . . . . .561
. . . . . . . . . . . .549
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Table 478. Cursor Interrupt Clear register (CRSR_INTCLR,
Table 479. Cursor Raw Interrupt Status register
Table 480. Cursor Masked Interrupt Status register
Table 481. FIFO bits for Little-endian Byte, Little-endian Pixel
Table 482. FIFO bits for Big-endian Byte, Big-endian Pixel
Table 483. FIFO bits for Little-endian Byte, Big-endian Pixel
Table 484. RGB mode data formats . . . . . . . . . . . . . . . . 569
Table 485. Palette data storage for TFT modes. . . . . . . 570
Table 486. Palette data storage for STN color modes. . . 570
Table 487. Palette data storage for STN monochrome mode.
Table 488. Palette data storage for STN monochrome mode.
Table 489. Addresses for 32 x 32 cursors . . . . . . . . . . . 574
Table 490. Buffer to pixel mapping for 32 x 32 pixel cursor
Table 491. Buffer to pixel mapping for 64 x 64 pixel cursor
Table 492. Pixel encoding. . . . . . . . . . . . . . . . . . . . . . . . 576
Table 493. Color display driven with 2 2/3 pixel data . . . 577
Table 494. LCD panel connections for STN single panel
Table 495. LCD panel connections for STN dual panel mode
Table 496. LCD panel connections for TFT panels. . . . . 585
Table 497. SCT clocking and power control . . . . . . . . . . 587
Table 498. SCT pin description . . . . . . . . . . . . . . . . . . . 589
Table 499. Register overview: State Configurable Timer
Table 500. SCT configuration register (CONFIG - address
Table 501. SCT control register (CTRL - address 0x4000
Table 502. SCT limit register (LIMIT - address 0x4000 0008)
Table 503. SCT halt condition register (HALT - address
Table 504. SCT stop condition register (STOP - address
Table 505. SCT start condition register (START - address
Table 506. SCT counter register (COUNT - address 0x4000
Table 507. SCT state register (STATE - address 0x4000
Table 508. SCT input register (INPUT - address 0x4000
Table 509. SCT match/capture registers mode register
address 0x4000 8C20) bit description . . . . . 561
address 0x4000 8C24) bit description . . . . . 562
(CRSR_INTRAW, address 0x4000 8C28) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
(CRSR_INTSTAT, address 0x4000 8C2C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 562
order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566
order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567
order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568
571
572
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583
584
(base address 0x4000 0000) . . . . . . . . . . . . 590
0x4000 0000) bit description . . . . . . . . . . . . 593
0004) bit description. . . . . . . . . . . . . . . . . . . . 595
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 596
0x4000 000C) bit description . . . . . . . . . . . . 596
0x4000 0010) bit description . . . . . . . . . . . . 597
0x4000 0014) bit description . . . . . . . . . . . . 597
0040) bit description. . . . . . . . . . . . . . . . . . . . 597
0044) bit description. . . . . . . . . . . . . . . . . . . . 598
0048) bit description. . . . . . . . . . . . . . . . . . . . 599
(REGMODE - address 0x4000 004C) bit
Chapter 43: Supplementary information
UM10430
© NXP B.V. 2011. All rights reserved.
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