LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 630

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
Table 543. Timer external match registers (EMR - addresses 0x4008 403C (TIMER0),
Bit
0
1
2
3
5:4
7:6
9:8
Symbol Value
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
0x4008 503C (TIMER1), 0x400C 303C (TIMER2), 0x400C 403C (TIMER3)) bit
description
All information provided in this document is subject to legal disclaimers.
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
Rev. 00.13 — 20 July 2011
Description
External Match 0. When a match occurs between the TC and
MR0, this bit can either toggle, go low, go high, or do nothing,
depending on bits 5:4 of this register. This bit can be driven
onto a MATn.0 pin, in a positive-logic manner (0 = low,
1 = high).
External Match 1. When a match occurs between the TC and
MR1, this bit can either toggle, go low, go high, or do nothing,
depending on bits 7:6 of this register. This bit can be driven
onto a MATn.1 pin, in a positive-logic manner (0 = low,
1 = high).
External Match 2. When a match occurs between the TC and
MR2, this bit can either toggle, go low, go high, or do nothing,
depending on bits 9:8 of this register. This bit can be driven
onto a MATn.0 pin, in a positive-logic manner (0 = low,
1 = high).
External Match 3. When a match occurs between the TC and
MR3, this bit can either toggle, go low, go high, or do nothing,
depending on bits 11:10 of this register. This bit can be driven
onto a MATn.0 pin, in a positive-logic manner (0 = low,
1 = high).
External Match Control 0. Determines the functionality of
External Match 0.
Do Nothing.
Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m
pin is HIGH if pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 1. Determines the functionality of
External Match 1.
Do Nothing.
Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m
pin is HIGH if pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 2. Determines the functionality of
External Match 2.
Do Nothing.
Clear the corresponding External Match bit/output to 0
(MATn.m pin is LOW if pinned out).
Set the corresponding External Match bit/output to 1 (MATn.m
pin is HIGH if pinned out).
Toggle the corresponding External Match bit/output.
Chapter 25: LPC18xx Timer0/1/2/3
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
00
00
00