LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 608

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
<Document ID>
User manual
24.6.22 SCT capture control registers 0 to 15 (REGMODEn bit = 1)
24.6.23 SCT event state mask registers 0 to 15
24.6.24 SCT event control registers 0 to 15
If UNIFY = 1 in the CONFIG register, only the _L bits are used.
If UNIFY = 0 in the CONFIG register, this register can be written to as two registers
CAPCTRLn_L (address 0x4000 4100 to 0x4000 413C) and CAPCTRLn_H (address
0x4000 4102 to 0x4000 413E). Both the L and H registers can be read or written in a
single 32-bit read or write operation, or they can be read or written individually.
Each Capture Control register (L, H, or unified 32-bit) controls which events load the
corresponding Capture register from the counter.
Table 522. SCT capture control registers 0 to 15 (CAPCTRL- address 0x4000 0200
Each event has one associated SCT event state mask register that allow this event to
happen in one or more states of the counter selected by the HEVENT bit in the
corresponding EVCTRLn register.
An event n is disabled when its EVSTATEMSKn register contains all zeros, since it is
masked regardless of the current state.
In simple applications that don’t use states, write 0x01 to this register to enable an event.
Since the state will always remain at its reset value of 0, this effectively permanently
state-enables this event.
Table 523. SCT event state mask registers 0 to 15 (EVSTATEMSK - addresses 0x4000 0300
This register defines the conditions for event n to occur, other than the state variable
which is defined by the state mask register above. Most events are associated with a
particular counter (high, low, or unified), in which case the event can depend on a match
to that register. The other possible ingredient of an event is a selected input or output
signal.
Bit
15:0
31:16
Bit
31:0
Symbol
CAPCONn_L
CAPCONn_H
Symbol
STATEMSKn
(CAPCTRL0) to 0x4000 023C (CAPCTRL15)) bit description (REGMODEn bit = 1)
(EVSTATEMSK0) to 0x4000 0378 (EVSTATEMSK15)) bit description
All information provided in this document is subject to legal disclaimers.
Description
If bit m is one, event n (n= 0 to 15) happens in state m of the
counter selected by the HEVENT bit (m = state number; state 0 =
bit 0, state 1= bit 1,..., state 31 = bit 31).
Rev. 00.13 — 20 July 2011
Description
If bit m is one, event m causes the CAPn_L (UNIFY = 0) or the
CAPn (UNIFY = 1) register to be loaded (event 0 = bit 0, event 1
= bit 1,..., event 15 = bit 15).
If bit m is one, event m causes the CAPn_H (UNIFY = 0)
register to be loaded (event 0 = bit 16, event 1 = bit 17,..., event
15 = bit 31).
Chapter 24: LPC18xx State Configurable Timer (SCT)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
Reset
value
0