LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 23

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 7.
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Table 8.
[1]
<Document ID>
User manual
Boot mode BOOT_SRC
Boot pins
UART
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
USB1
SPI (SSP)
USART3
Boot mode
USART0
SPIFI
EMC 8-bit
EMC 16-bit
EMC 32-bit
USB0
USB1
SPI (SSP)
USART3
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI.
Boot mode when OTP BOOT_SRC bits are programmed
Boot mode when OPT BOOT_SRC bits are zero
bit 3
0
0
0
0
0
0
0
0
1
1
P2_9
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
HIGH
BOOT_SRC
bit 2
0
0
0
0
1
1
1
1
0
0
P2_8
LOW
LOW
LOW
LOW
HIGH
HIGH
HIGH
HIGH
LOW
P1_2
LOW
LOW
HIGH
HIGH
LOW
LOW
HIGH
HIGH
LOW
All information provided in this document is subject to legal disclaimers.
BOOT_SRC
bit 1
0
0
1
1
0
0
1
1
0
0
P1_1
LOW
HIGH Boot from Quad SPI flash connected to the SPIFI interface on
LOW
HIGH Boot from external static memory (such as NOR flash) using CS0
LOW
HIGH Boot from USB0.
LOW
HIGH Boot from SPI flash connected to the SSP0 interface on P3_3,
LOW
Rev. 00.13 — 20 July 2011
Description
Boot from device connected to USART0 using pins P2_0 and
P2_1.
P3_3 to P3_8
Boot from external static memory (such as NOR flash) using CS0
and an 8-bit data bus.
and a 16-bit data bus.
Boot from external static memory (such as NOR flash) using CS0
and a 32-bit data bus.
Boot from USB1.
P3_6, P3_7 and P3_8
Boot from device connected to USART3 using pins P2_3 and
P2_4.
BOOT_SRC
bit 0
0
1
0
1
0
1
0
1
0
1
[1]
Description
Boot source is defined by the reset state of P1_1,
P1_2, and P2_8 pins. See
Boot from device connected to USART0 using pins
P2_0 and P2_1.
Boot from Quad SPI flash connected to the SPIFI
interface using pins P3_3 to P3_8.
Boot from external static memory (such as NOR
flash) using CS0 and an 8-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 16-bit data bus.
Boot from external static memory (such as NOR
flash) using CS0 and a 32-bit data bus.
Boot from USB0.
Boot from USB1.
Boot from SPI flash connected to the SSP0
interface on P3_3, P3_6, P3_7 and P3_8
Boot from device connected to USART3 using pins
P2_3 and P2_4.
.
[1]
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Chapter 3: LPC18xx Boot ROM
Table
UM10430
© NXP B.V. 2011. All rights reserved.
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