LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 677

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

NXP Semiconductors
Table 596: QEI Interrupt Enable Clear register (IEC - address 0x400C 6FD8) bit description
Table 597: QEI Interrupt Enable Set register (IES - address 0x400C 6FDC) bit description
<Document ID>
User manual
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
31:16
Bit
0
1
2
3
4
5
6
7
Symbol
INX_EN
TIM_EN
VELC_EN
DIR_EN
ERR_EN
ENCLK_EN
POS0_Int
POS1_Int
POS2_Int
REV_Int
POS0REV_Int Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set
POS1REV_Int Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set
POS2REV_Int Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set
REV1_Int
REV2_Int
MAXPOS_Int
-
Symbol
INX_EN
TIM_EN
VELC_EN
DIR_EN
ERR_EN
ENCLK_EN
POS0_Int
POS1_Int
27.6.3.1 QEI Interrupt Enable Clear register
27.6.3.2 QEI Interrupt Enable Set register
27.6.3 Interrupt registers
Writing a 1 to a bit in this register clears the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Indicates that an index pulse was detected.
Indicates that and encoder clock pulse was detected.
Indicates that the position 0 compare value is equal to the current position.
Indicates that the position 1compare value is equal to the current position.
Indicates that the position 2 compare value is equal to the current position.
Reserved
Writing a 1 to a bit in this register sets the corresponding bit in the QEI Interrupt Enable
register (QEIIE).
Description
Indicates that a velocity timer overflow occurred
Indicates that captured velocity is less than compare velocity.
Indicates that a change of direction was detected.
Indicates that an encoder phase error was detected.
Indicates that the index compare value is equal to the current index count.
and the REV_Int is set.
and the REV_Int is set.
and the REV_Int is set.
Indicates that the index 1 compare value is equal to the current index count.
Indicates that the index 2 compare value is equal to the current index count.
Indicates that the current position count goes through the MAXPOS value to zero in
forward direction, or through zero to MAXPOS in backward direction.
Description
Indicates that an index pulse was detected.
Indicates that a velocity timer overflow occurred
Indicates that captured velocity is less than compare velocity.
Indicates that a change of direction was detected.
Indicates that an encoder phase error was detected.
Indicates that and encoder clock pulse was detected.
Indicates that the position 0 compare value is equal to the current position.
Indicates that the position 1compare value is equal to the current position.
All information provided in this document is subject to legal disclaimers.
Rev. 00.13 — 20 July 2011
Chapter 27: LPC18xx Quadrature Encoder Interface (QEI)
UM10430
© NXP B.V. 2011. All rights reserved.
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Reset
value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
value
0
0
0
0
0
0
0
0