LPC1837FET256,551 NXP Semiconductors, LPC1837FET256,551 Datasheet - Page 712

• Manufacturer Part Number: LPC1837FET256,551
• Description: Microcontrollers (MCU) 32BIT ARM CORTEX-M3 MCU 136KB SRAM
• Manufacturer: NXP Semiconductors
• Series: LPC18xxr

Specifications of LPC1837FET256,551

• Core: ARM Cortex M3
• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 150MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, Microwire, SD/MMC, SPI, SSI, SSP, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, I²S, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 136K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b; D/A 1x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-LBGA
• Lead Free Status / Rohs Status: Details
• Other names: 935293795551

32.1 How to read this chapter
32.2 Basic configuration
32.3 Features
<Document ID>
User manual
The USART0/2/3 controllers are available on all LPC18xx parts.
The USART0/2/3 are configured as follows:
Table 661. USART0/2/3 clocking and power control
USART0 clock to register interface
USART0 peripheral clock (PCLK)
USART2 clock to register interface
USART2 peripheral clock (PCLK)
USART3 clock to register interface
USART3 peripheral clock (PCLK)
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UM10430
Chapter 32: LPC18xx USART0_2_3
Rev. 00.13 — 20 July 2011
See
The USART0/2/3 are reset by the UART0/2/3_RST (reset #44/46/47).
The USART0/2/3 interrupts are connected to slots # 24/26/27 in the NVIC.
For connecting the USART0/2/3 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see
in the DMA Channel Configuration registers
16-byte receive and transmit FIFOs.
Register locations conform to ‘550 industry standard.
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
Built-in baud rate generator.
UART allows for implementation of either software or hardware flow control.
RS-485/EIA-485 9-bit mode support with output enable.
Support for synchronous mode UART (USART).
IrDA interface (USART3 only).
DMA support.
Smart Card interface.
Table 661
All information provided in this document is subject to legal disclaimers.
for clocking and power control.
Rev. 00.13 — 20 July 2011
Base clock
BASE_M3_CLK
BASE_UART0_CLK CLK_APB0_UART0 150 MHz
BASE_M3_CLK
BASE_UART2_CLK CLK_APB2_UART2 150 MHz
BASE_M3_CLK
BASE_UART3_CLK CLK_APB2_UART3 150 MHz
Table
(Section
35) and enable the GPDMA channel
16.6.20).
Branch clock
CLK_M3_UART0
CLK_M3_UART2
CLK_M3_UART3
© NXP B.V. 2011. All rights reserved.
User manual
Maximum
frequency
150 MHz
150 MHz
150 MHz
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