IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 97

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Clocked Video Output
Clocked Video Output
January 2011 Altera Corporation
f
Refer to the SMPTE 2016-1-2007 standard for a more detailed description of the AFD
codes.
Table 5–11
Table 5–11. AFD Extractor Register Map
The Clocked Video Output MegaCore function converts Avalon-ST Video to clocked
video formats (such as BT656, BT1120, and DVI). It formats Avalon-ST Video into
clocked video by inserting horizontal and vertical blanking and generating horizontal
and vertical synchronization information using the Avalon-ST Video control and
active picture packets.
No conversion is done to the active picture data, the color plane information remains
the same as in the Avalon-ST Video format.
The Clocked Video Output MegaCore function converts data from the flow controlled
Avalon-ST Video protocol to clocked video. It also provides clock crossing capabilities
to allow video formats running at different frequencies to be output from the system.
In addition, this MegaCore function provides a number of configuration registers that
control the format of video leaving the system (blanking period size, synchronization
length, and interlaced or progressive mode) and a status interrupt that can be used to
determine when the video format changes.
Address
0
1
2
3
4
5
6
7
8
shows the AFD Extractor register map.
Bar data value 1
Bar data value 2
Bar data flags
AFD valid
Register
Interrupt
Control
AFD
AR
When bit 0 is 0, the core discards all packets.
When bit 0 is 1, the core passes through all non-
ancillary packets.
Reserved.
When bit 1 is 1, a change to the AFD data has been
detected and the interrupt has been set. Writing a 1 to
bit 1 clears the interrupt.
Bits 0-3 contain the active format description code.
Bit 0 contains the aspect ratio code.
When AFD is 0000 or 0100, bits 0-3 describe the
contents of bar data value 1 and bar data value 2.
When AFD is 0011, bar data value 1 is the pixel number
end of the left bar and bar data value 2 is the pixel
number start of the right bar.
When AFD is 1100, bar data value 1 is the line number
end of top bar and bar data value 2 is the line number
start of bottom bar.
Bits 0-15 contain bar data value 1
Bits 0-15 contain bar data value 2
When bit 0 is 0, an AFD packet is not present for each
image packet.
When bit 0 is 1, an AFD packet is present for each
image packet.
Video and Image Processing Suite User Guide
Description
5–17