IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 162

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–6
Table 6–6. Clocked Video Input Signals (Part 2 of 3)
Video and Image Processing Suite User Guide
av_readdata
av_write
av_writedata
is_clk
is_data
is_eop
is_ready
is_sop
is_valid
overflow
refclk_div
sof
sof_locked
status_update_int
vid_data
vid_datavalid
vid_f
vid_h_sync
vid_hd_sdn
Signal
Direction
Out
In
In
In
Out
Out
In
Out
Out
Out
Out
Out
Out
Out
In
In
In
In
In
control slave port Avalon-MM read data bus. These output lines are used for read
transfers.
control slave port Avalon-MM write signal. When this signal is asserted, the
control port accepts new data from the write data bus.
control slave port Avalon-MM write data bus. These input lines are used for write
transfers.
Clock signal for Avalon-ST ports dout and control. The MegaCore function
operates on the rising edge of the is_clk signal.
dout port Avalon-ST data bus. Pixel data is transferred out of the MegaCore
function over this bus.
dout port Avalon-ST endofpacket signal. This signal is asserted when the
MegaCore function is ending a frame.
dout port Avalon-ST ready signal. This signal is asserted by the downstream device
when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal is asserted when the
MegaCore function is starting a new frame.
dout port Avalon-ST valid signal. This signal is asserted when the MegaCore
function outputs data.
Clocked video overflow signal. A signal corresponding to the overflow sticky bit of
the Status register synchronized to vid_clk. This signal is for information only
and no action is required if it is asserted.
A divided down version of vid_clk (refclk). Setting the Refclk Divider register
to be the number of samples in a line produces a horizontal reference on this signal
that a PLL can use to synchronize its output clock.
Start of frame signal. A change of 0 to 1 indicates the start of the video frame as
configured by the SOF registers. Connecting this signal to a Clocked Video Output
MegaCore function allows the function to synchronize its output video to this
signal.
Start of frame locked signal. When high the sof signal is valid and can be used.
control slave port Avalon-MM interrupt signal. When asserted the status registers
of the MegaCore function have been updated and the master should read them to
determine what has occurred.
Clocked video data bus. Video data is transferred into the MegaCore function over
this bus.
Clocked video data valid signal. This signal is asserted when a valid sample of video
data is present on vid_data.
(Separate Synchronization Mode Only.) Clocked video field signal. For interlaced
input, this signal distinguishes between field 0 and field 1. For progressive video,
this signal should be deasserted.
(Separate Synchronization Mode Only.) Clocked video horizontal synchronization
signal. This signal is asserted during the horizontal synchronization period of the
video stream.
Clocked video color plane format selection signal (in run-time switching of color
plane transmission formats mode only). This signal distinguishes between
sequential (when low) and parallel (when high) color plane formats.
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Description
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January 2011 Altera Corporation
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Clocked Video Input
Chapter 6: Signals