IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 181

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2D FIR Filter
Table 7–1. 2D FIR Filter Control Register Map
Alpha Blending Mixer
January 2011 Altera Corporation
0
1
2
3
4
n
Address
Control
Status
Coefficient 0
Coefficient 1
Coefficient 2
Coefficient n
Register Name
The 2D FIR Filter, Alpha Blending Mixer, Clipper, Clocked Video Input, Clocked
Video Output, Color Space Converter, Control Synchronizer, Deinterlacer, Frame
Buffer, Frame Reader, Gamma Corrector, Interlacer, Scaler, Scaler II, and Test Pattern
Generator MegaCore functions support run-time control for some of their behavior
using a common type of Avalon-MM slave interface. This chapter describes the
control register maps which can be accessed using these interfaces.
For information about the Control and Status registers which are common to these
interfaces, refer to
Table 7–1
The width of each register in the 2D FIR Filter control register map is 32 bits. The
coefficient registers use integer, signed 2’s complement numbers. To convert from
fractional values, simply move the binary point right by the number of fractional bits
specified in the user interface.
The control data is read once at the start of each frame and is buffered inside the
MegaCore function, so the registers can be safely updated during the processing of a
frame.
Table 7–2
map.
describes the control register map for the 2D FIR Filter MegaCore function.
describes the Alpha Blending Mixer MegaCore function control register
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes
the 2D FIR Filter MegaCore function to stop the next time control information is read.
Refer to
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
The coefficient at the top left (origin) of the filter kernel.
The coefficient at the origin across to the right by one.
The coefficient at the origin across to the right by two.
The coefficient at position:
■
■
Row (where 0 is the top row of the kernel) is the integer value via the truncation of
(n–2) / (filter kernel width)
Column (where 0 is the far left row of the kernel) is the remainder of
(n–2) / (filter kernel width)
“Avalon-MM Slave Interfaces” on page 4–17
“Avalon-MM Slave Interfaces” on page
for full details.
Description
7. Control Register Maps
Video and Image Processing Suite User Guide
for full details.
4–17.
“Avalon-MM