IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 30

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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Video and Image Processing Suite User Guide
Simulate the IP Core
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6. If the parameter editor includes EDA and Summary tabs, follow these steps:
7. Click the Finish button, the parameter editor generates the top-level HDL code for
8. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current
You can now integrate your custom IP core instance in your design, simulate, and
compile. While integrating your IP core instance into your design, you must make
appropriate pin assignments. You can create virtual pin to avoid making specific pin
assignments for top-level signals while you are simulating and not ready to map the
design to hardware.
For some IP cores, the generation process also creates a complete example design in
the <variation_name>_example_design_fileset/example_project/ directory. This
example demonstrates how to instantiate and connect the IP core.
For information about the Quartus II software, including virtual pins and the
MegaWizard Plug-In Manager, refer to Quartus II Help.
You can simulate your IP core variation with the functional simulation model and the
testbench or example design generated with your IP core. The functional simulation
model and testbench files are generated in a project subdirectory. This directory may
also include scripts to compile and run the testbench.
For a complete list of models or libraries required to simulate your IP core, refer to the
scripts provided with the testbench.
For more information about simulating Altera IP cores, refer to
Designs
a. Some third-party synthesis tools can use a netlist that contains the structure of
b. On the Summary tab, if available, select the files you want to generate. A gray
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your IP core, and a simulation directory which includes files for simulation.
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Quartus II project. You can also turn on Automatically add Quartus II IP Files to
all projects.
an IP core but no detailed logic to optimize timing and performance of the
design containing it. To use this feature if your synthesis tool and IP core
support it, turn on Generate netlist.
checkmark indicates a file that is automatically generated. All other files are
optional.
in volume 3 of the Quartus II Handbook.
If file selection is supported for your IP core, after you generate the core, a
generation report (<variation name>.html) appears in your project directory.
This file contains information about the generated files.
The Finish button may be unavailable until all parameterization errors
listed in the messages window are corrected.
Chapter 2: Getting Started with Altera IP Cores
MegaWizard Plug-In Manager Flow
January 2011 Altera Corporation
Simulating Altera