IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 179

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 6: Signals
Test Pattern Generator
Test Pattern Generator
Table 6–19. Test Pattern Generator Signals
January 2011 Altera Corporation
clock
reset
control_av_address
control_av_chipselect
control_av_readdata
control_av_write
control_av_writedata
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
Note to
(1) These ports are present only if Runtime control of image size is on in the parameter editor.
Table 6–19
Signal
Table 6–19
MegaCore function.
Direction
In
In
In
In
Out
In
In
Out
Out
In
Out
Out
shows the input and output signals for the Test Pattern Generator
The main system clock. The MegaCore function operates on the rising edge
of the clock signal.
The MegaCore function is asynchronously reset when reset is asserted
high. The reset must be de-asserted synchronously with respect to the rising
edge of the clock signal.
control slave port Avalon-MM address bus. Specifies a word offset into
the slave address space.
control slave port Avalon-MM chipselect signal. The control port
ignores all other signals unless this signal is asserted.
control slave port Avalon-MM readdata bus. These output lines are used
for read transfers.
control slave port Avalon-MM write signal. When this signal is asserted,
the control port accepts new data from the writedata bus.
control slave port Avalon-MM writedata bus. These input lines are used
for write transfers.
dout port Avalon-ST data bus. Pixel data is transferred out of the MegaCore
function over this bus.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
(1)
(1)
(1)
Description
Video and Image Processing Suite User Guide
(1)
(1)
6–23