IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 108

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–28
Figure 5–13. Example System Connections
Video and Image Processing Suite User Guide
FPGA
Underflow
SDI
RX
Figure 5–13
Clocked Video Output MegaCore functions to a video PLL.
Moving between flow controlled Avalon-ST Video and clocked video can cause
problems if the flow controlled video does not provide data at a rate fast enough to
satisfy the demands of the outgoing clocked video.
The Clocked Video Output MegaCore function contains a FIFO that, when set to a
large enough value, can accommodate any “burstiness” in the flow data, as long as
the output rate of the downstream Avalon-ST Video components is equal to or higher
than that of the outgoing clocked video.
If this is not the case, the FIFO underflows. If underflow occurs, the MegaCore
function continues to output video and re-syncs the startofpacket, for the next
image packet, from the Avalon-ST Video interface with the start of the next frame.
The underflow can be detected by looking at bit 2 of the Status register. This bit is
sticky and if an underflow occurs, stays at 1 until the bit is cleared by writing a 1 to it.
In addition to the underflow bit, the current level of the FIFO can be read from the
Used Words register.
Clocked
Video
Input
refclk_div
Video PLL
shows an example of how to connect the Clocked Video Input and
Divider
Detector
+
Phase
sof_locked
-
sof
Feedback
Charge
Divider
Pump
Clocked
Video
Output
27 MHz
VCXO
Chapter 5: Functional Descriptions
vid_clk
January 2011 Altera Corporation
Clocked Video Output
SDI
TX