IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 185

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Clocked Video Output
Clocked Video Output
Table 7–5. Clocked Video Output Control Register Map (Part 1 of 2)
January 2011 Altera Corporation
0
1
2
3
4
5
6
7
8
Address
Control
Status
Interrupt
Used Words
Video Mode Match
ModeX Control
Mode1 Sample Count
Mode1 F0 Line Count
Mode1 F1 Line Count
Register
Table 7–5
map. The width of each register is 16 bits.
describes the Clocked Video Output MegaCore function control register
Bit 0 of this register is the Go bit:
■
Bits 3, 2, and 1 of the Control register are the interrupt enables:
■
■
■
■
Bit 0 of this register is the Status bit:
■
Bit 1 of the Status register is unused.
Bit 2 is the underflow sticky bit:
■
Bit 3 is the frame locked bit.
■
Bits 2 and 1 are the interrupt status bits:
■
■
■
The used words level of the output FIFO.
One-hot register that indicates the video mode that is selected.
Video Mode 1 Control. Bit 0 of this register is the Interlaced bit:
■
Bit 1 of this register is the sequential output control bit (only if the Allow output
of color planes in sequence compile-time parameter is enabled).
■
Video mode 1 sample count. Specifies the active picture width of the field.
Video mode 1 field 0/progressive line count. Specifies the active picture height
of the field.
Video mode 1 field 1 line count (interlaced video only). Specifies the active
picture height of the field.
Setting this bit to 1 causes the Clocked Video Output MegaCore function to
start video data output. Refer to
Setting bit 1 to 1, enables the status update interrupt.
Setting bit 2 to 1, enables the locked interrupt.
Setting bit 3 to 1, enables the synchronization outputs (vid_sof,
vid_sof_locked, vcoclk_div).
When bit 3 is set to 1, setting bit 4 to 1, enables frame locking. The Clock
Video Output attempts to align its vid_sof signal to the sof signal from the
Clocked Video Input MegaCore function.
Data is being output by the Clocked Video Output MegaCore function when
this bit is asserted. Refer to
When bit 2 is asserted, the output FIFO has underflowed. The underflow
sticky bit stays asserted until a 1 is written to this bit.
When bit 3 is asserted, the Clocked Video Output has aligned its start of
frame to the incoming sof signal.
When bit 1 is asserted, the status update interrupt has triggered.
When bit 2 is asserted, the locked interrupt has triggered.
The interrupts stay asserted until a write of 1 is performed to these bits.
Set to 1 for interlaced. Set to a 0 for progressive.
Setting bit 1 to 1, enables sequential output from the Clocked Video Output
e.g. for NTSC. Setting bit 1 to a 0, enables parallel output from the Clocked
Video Output e.g. for 1080p.
“Control Port” on page 5–21
Description
“Control Port” on page 5–21
Video and Image Processing Suite User Guide
for full details.
for full details.
7–5