IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 22

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–14
Table 1–15. Frame Buffer Performance (Part 2 of 2)
Table 1–16. Frame Reader Performance
Video and Image Processing Suite User Guide
Triple-buffering VGA (640×480) 8-bit RGB with a parallel data interface.
Triple-buffering VGA (640×480) 8-bit RGB buffering up to 32 large Avalon-ST Video packets into RAM.
Triple-buffering 720×576 8-bit RGB with sequential data interface and runtime control interface.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Reading a video frame (1920x1080) through master port width of 256 and producing output with 4 channels in parallel,
8-bit data.
Reading a video frame (1024x768) through master port width of 256 and producing output with 2 channels in parallel,
10-bit data.
Reading a video frame through master port width of 256 and producing output with 1 channel in sequence and 1 channel in
parallel, 8-bit data.
Reading a video frame through master port width of 128 and outputs them with 1 channel in sequence and 1 channel in
parallel, 8-bit data.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Frame Reader
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1–15:
1–15:
(1)
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Table 1–16
LUTs/ALUTs
LUTs/ALUTs
1,287
2,292
1,285
1,286
1,596
1,521
1,460
1,317
891
932
938
905
836
842
shows the performance figures for the Frame Reader.
Registers
Registers
Logic
1,663
1,354
3,881
3,291
1,684
1,314
Logic
2,107
1,821
2,041
1,763
1,968
1,699
1,830
1,562
11,168
11,168
32,870
32,870
30,820
30,820
32,854
32,854
16,472
16,472
7,168
7,168
8,192
8,192
Bits
Bits
Memory
Memory
M9K
M9K
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Chapter 1: About This MegaCore Function Suite
(9×9)
(9×9)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DSP Blocks
DSP Blocks
Performance and Resource Utilization
January 2011 Altera Corporation
(18×18)
(18×18)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
170.94
321.65
166.67
301.11
179.21
329.92
153.07
287.85
163.93
295.77
162.44
289.10
169.15
310.85
(MHz)
(MHz)
f
f
MAX
MAX