IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 105

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 5: Functional Descriptions
Clocked Video Output
Table 5–14. Interlaced Frame Parameter Descriptions
January 2011 Altera Corporation
ModeN Control
ModeN Sample Count
ModeN F0 Line Count
ModeN F1 Line Count
ModeN Horizontal Front
Porch
ModeN Horizontal Sync
Length
ModeN Horizontal
Blanking
ModeN Vertical Front
Porch
ModeN Vertical Sync
Length
ModeN Vertical Blanking
ModeNF0 Vertical Front
Porch
ModeN F0 Vertical Sync
Length
ModeN F0 Vertical
Blanking
ModeN Active Picture
Line
ModeN F0 Vertical Rising
ModeN Field Rising
ModeN Field Falling
ModeN Valid
ModeN Ancillary Line
ModeN F0 Ancillary Line
Register Name
Table 5–14
N/A
Active samples
F0 active lines
F1 active lines
H front porch
H sync
H blanking
V front porch
V sync
V blanking
F0 V front porch
F0 V sync
F0 V blank
active picture line
F0 V rising edge
line
F rising edge line
F falling edge line
N/A
Ancillary line
F0 ancillary line
Parameter
shows how
The zeroth bit of this register is the Interlaced bit:
■
■
■
The width of the active picture region in samples/pixels.
The height of the active picture region for field F0 in lines.
The height of the active picture region for field F1 in lines.
(Separate synchronization mode only.) The front porch of the horizontal
synchronization (the low period before the synchronization starts).
(Separate synchronization mode only.) The synchronization length of the
horizontal synchronization (the high period of the sync).
The horizontal blanking period (non active picture portion of a line).
(Separate synchronization mode only.) The front porch of the vertical
synchronization (the low period before the synchronization starts) for field
F1.
(Separate synchronization mode only.) The synchronization length of the
vertical synchronization (the high period of the sync) for field F1.
The vertical blanking period (non active picture portion of a frame) for field
F1.
(Separate synchronization mode only.) The front porch of the vertical
synchronization (the low period before the synchronization starts) for field
F0.
(Separate synchronization mode only.) The synchronization length of the
vertical synchronization (the high period of the sync) for field F0.
The vertical blanking period (non active picture portion of a frame) for field
F0.
The line number that the active picture starts on. For non SDI output this
can be left at 0.
The line number that the vertical blanking period for field F0 begins on.
The line number that field F1 begins on.
The line number that field F0 begins on.
Set to enable the mode after the configuration is complete.
(Embedded synchronization mode only.) The line to start inserting ancillary
packets.
(Embedded synchronization mode only.) The line in field F0 to start
inserting ancillary packets.
Figure 5–11
Set to 0 for interlaced.
Bit 1 of this register is the sequential output control bit (only if the Allow
output of color planes in sequence compile-time parameter is enabled).
Setting bit 1 to 1, enables sequential output from the Clocked Video
Output, such as for NTSC. Setting bit 1 to a 0, enables parallel output
from the Clocked Video Output, such as for 1080p.
relates to the register map.
Description
Video and Image Processing Suite User Guide
5–25