IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 187

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Color Space Converter
Color Space Converter
Table 7–6. Color Space Converter Control Register Map
Control Synchronizer
Table 7–7. Control Synchronizer Control Register Map (Part 1 of 2)
January 2011 Altera Corporation
0
1
2
3
4
5
6
7
8
9
10
11
12
13
0
1
Address
Address
Control
Status
Coefficient A0
Coefficient B0
Coefficient C0
Coefficient A1
Coefficient B1
Coefficient C1
Coefficient A2
Coefficient B2
Coefficient C2
Summand S0
Summand S1
Summand S2
Control
Status
Register Name
Register(s)
Table 7–6
function.
The width of each register in the Color Space Converter control register map is 32 bits.
The coefficient and summand registers use integer, signed 2’s complement numbers.
To convert from fractional values, simply move the binary point right by the number
of fractional bits specified in the user interface.
The control data is read once at the start of each frame and is buffered inside the
MegaCore function, so the registers can be safely updated during the processing of a
frame.
The width of each register of the frame reader is 32 bits. The control data is read once
at the start of each frame. The registers may be safely updated during the processing
of a frame.
register map.
Bit 0 of this register is the Go bit. Setting this bit to 1 causes the Control Synchronizer
MegaCore function to start passing through data. Bit 1 of the Control register is the
interrupt enable. Setting bit 1 to 1, enables the completion of writes interrupt.
Bit 0 of this register is the Status bit. All other bits are unused. Refer to
Slave Interfaces” on page 4–17
describes the control register map for the Color Space Converter MegaCore
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes
the Color Space Converter MegaCore function to stop the next time control information
is read. Refer to
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
For details, refer to
Table 7–7
describes the Control Synchronizer MegaCore function control
“Avalon-MM Slave Interfaces” on page 4–17
“Color Space Conversion” on page
for full details.
for full details.
Description
Description
Video and Image Processing Suite User Guide
5–33.
for full details.
“Avalon-MM
“Avalon-MM
7–7