IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 25

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function Suite
Performance and Resource Utilization
Table 1–20. Scaler II Performance (Part 2 of 2)
Table 1–21. Switch Performance
Table 1–22. Test Pattern Generator Performance (Part 1 of 2)
January 2011 Altera Corporation
Scaling up or down between NTSC standard definition and 1080 pixel high definition using 10 taps horizontally and 9
vertically. Resolution and coefficients are set by a run-time control interface.
Scaling NTSC standard definition (720x480) RGB to high definition 1080p using a bicubic algorithm.
Notes to
(1) EP4CGX22CF19C6 devices.
(2) 5SGXEA7H3F35C3 devices.
2 input, 2 output switch with alpha channels disabled and doing three colors in sequence.
12 input, 12 output switch with alpha channels enabled and doing three colors in parallel.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Producing a 400×x200, 8-bit 4:2:0 Y'Cb'Cr' stream with a parallel data interface.
Producing a 640×480, 8-bit R'G'B' stream with a sequential data interface.
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Switch
Test Pattern Generator
(2)
(2)
(2)
(2)
(2)
(2)
1–20:
1–21:
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Combinational
Table 1–21
Table 1–22
LUTs/ALUTs
LUTs/ALUTs
LUTs/ALUTs
6,177
4,553
2,839
1,698
1,397
122
159
152
214
161
964
80
shows the performance figures for the Switch.
shows the performance figures for the Test Pattern Generator.
Registers
Registers
Registers
Logic
6,884
2,547
Logic
4,016
3,101
1,909
1,407
Logic
155
127
168
115
217
117
417,936
417,936
70,512
70,512
Bits
Bits
192
192
192
192
Bits
—
—
—
—
Memory
Memory
Memory
M9K
M9K
M9K
—
—
—
—
—
—
—
—
—
—
—
—
Video and Image Processing Suite User Guide
(9×9)
(9×9)
(9×9)
—
—
—
—
—
—
—
—
29
—
12
—
DSP Blocks
DSP Blocks
DSP Blocks
(18×18)
(18×18)
(18×18)
—
—
—
—
—
—
—
—
—
10
—
4
328.95
527.43
165.34
231.70
315.06
500.00
315.06
490.44
156.37
326.37
167.34
349.53
(MHz)
(MHz)
(MHz)
f
f
f
MAX
MAX
MAX
1–17