IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 100

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

5–20
Video and Image Processing Suite User Guide
Figure 5–9. Interlaced Frame Format
Embedded Synchronization Format
For the embedded synchronization format, the MegaCore function inserts the
horizontal and vertical syncs and field into the data stream during the horizontal
blanking period
A sample is output for each clock cycle on the vid_data bus.
There are two extra signals that are only used when connecting to the SDI MegaCore
function. They are vid_trs, which is high during the 3FF sample of the TRS, and
vid_ln, which outputs the current SDI line number. These are used by the SDI
MegaCore function to insert line numbers and cyclical redundancy checks (CRC) into
the SDI stream as specified in the 1.5 Gbps HD SDI and 3 Gbps SDI standards.
The Clocked Video Output MegaCore inserts any ancillary packets (packets with a
type of 13 or 0xD) into the output video during the vertical blanking. For information
about Avalon-ST Video ancillary data packets, refer to
page
lines specified in its parameters or mode registers (ModeN Ancillary Line and ModeN
F0 Ancillary Line). The Clocked Video Output MegaCore stops inserting the packets
at the end of the vertical blanking.
4–10. The Clocked Video Output MegaCore begins inserting the packets on the
(Table 5–6 on page
F0 Vertical Blanking
Horizontal Sync
Vertical Blanking
F0 Active Picture
F1 Active Picture
5–11).
Width
Width
“Ancillary Data Packets” on
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Clocked Video Output