IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 21

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 1: About This MegaCore Function Suite
Performance and Resource Utilization
Table 1–13. Control Synchronizer Performance (Part 2 of 2)
Table 1–14. Deinterlacer Performance
Table 1–15. Frame Buffer Performance (Part 1 of 2)
January 2011 Altera Corporation
control data entries that can be written to other cores is 3.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Deinterlacing 64×64 pixel 8-bit R’G’B’ frames using the bob algorithm with scanline duplication.
Deinterlacing with scanline interpolation using the bob algorithm working on 352×288 pixel 12-bit Y’CbCr 4:2:2 frames.
Deinterlacing PAL (720×576) with 8-bit Y'CbCr 4:4:4 color using the motion-adaptive algorithm.
Deinterlacing HDTV 1080i resolution with 12-bit Y’CbCr 4:4:4 color using the weave algorithm.
Notes to
(1) EP4CGX15BF14C6 devices.
(2) 5SGXEA7H3F35C3 devices.
Double-buffering XGA (1024×768) 8-bit RGB with a sequential data interface.
Synchronizing the configuration of other MegaCore functions with 3 channels in sequence, and the maximum number of
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Cyclone IV GX
Device Family
Device Family
Device Family
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Stratix V
Table
Table
Deinterlacer
Frame Buffer
(2)
(2)
(2)
(2)
(2)
(2)
1–22:
1–14:
(1)
(1)
(1)
(1)
(1)
(1)
Combinational
Combinational
Combinational
Table 1–14
Table 1–15
LUTs/ALUTs
LUTs/ALUTs
LUTs/ALUTs
6,992
5,188
2,790
2,144
1,489
1,100
525
389
632
454
594
398
shows the performance figures for the Deinterlacer.
shows the performance figures for the Frame Buffer.
Registers
Registers
Registers
Logic
9,697
7,879
3,313
2,299
Logic
Logic
1,942
1,487
582
332
704
398
750
398
ALUTs
—
—
—
—
—
—
—
—
7,936
7,936
Bits
Bits
—
—
Memory
Memory
Memory
157,372
157,372
17,280
17,280
14,400
14,400
2,566
2,566
Bits
M9K
M9K
—
—
—
—
M9K
—
—
—
—
—
—
—
—
Video and Image Processing Suite User Guide
(9×9)
(9×9)
—
—
—
—
DSP Blocks
DSP Blocks
(9×9)
—
—
—
—
—
—
—
4
DSP Blocks
(18×18)
(18×18)
(18×18)
—
—
—
—
—
—
—
—
—
—
—
2
212.18
377.93
175.59
281.69
(MHz)
(MHz)
204.83
294.55
202.18
303.58
135.15
219.68
176.03
283.61
f
f
(MHz)
MAX
MAX
f
MAX
1–13