IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 189

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 7: Control Register Maps
Frame Buffer
Table 7–8. Deinterlacer Control Register Map for Run-Time Control of the Motion-Adaptive Algorithm
Table 7–9. Deinterlacer Control Register Map for Synchronizing the Input and Output Frame Rates
Frame Buffer
January 2011 Altera Corporation
0
1
2
3
0
1
2
3
Note to
(1) The behavior of the rate conversion algorithm is not directly affected by a particular choice of input and output rates but only by their ratio.
Address
Address
23.976 -> 29.970 is equivalent to 24 -> 30.
Table
Control
Status
Motion value
override
Blending
coefficient
Control
Status
Input frame
rate
Output frame
rate
7–9:
Register
Register
Table 7–8
algorithm at run time. The control data is read once and registered before outputting a
frame. It can be safely updated during the processing of a frame.
Table 7–8
frame rates. The control data is read and registered when receiving the image data
header that signals new frame. It can be safely updated during the processing of a
frame.
A run-time control can be attached either to the writer component or to the reader
component of the Frame Buffer MegaCore function but not to both. The width of each
register is 16 bits.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the
Deinterlacer MegaCore function to stop before control information is read and before
outputting a frame. While stopped, the Deinterlacer may continue to receive and drop
frames at its input if triple-buffering is enabled. Refer to
page 4–17
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
Write-only register. Bit 0 of this register should be set to 1 to override the per-pixel
motion value computed by the deinterlacing algorithm with a user specified value. This
register cannot be read.
Write-only register. The 16-bit value that overrides the motion value computed by the
deinterlacing algorithm. This value can vary between 0 (weaving) to 65535 (bobbing).
The register cannot be read.
Bit 0 of this register is the Go bit, all other bits are unused. Setting this bit to 0 causes the
Deinterlacer MegaCore function to stop before control information is read and before
receiving and buffering the next frame. While stopped, the Deinterlacer may freeze the
output and repeat a static frame if triple-buffering is enabled. Refer to
Interfaces” on page 4–17
Bit 0 of this register is the Status bit, all other bits are unused. Refer to
Slave Interfaces” on page 4–17
Write-only register. An 8-bit integer value for the input frame rate This register cannot be
read.
Write-only register. An 8-bit integer value for the output frame rate. The register cannot be
read.
describes the control register map that controls the motion-adaptive
describes the control register map that synchronizes the input and output
(1)
(1)
for full details.
for full details.
for full details.
for full details.
Description
Description
Video and Image Processing Suite User Guide
“Avalon-MM Slave Interfaces” on
“Avalon-MM Slave
“Avalon-MM
“Avalon-MM
7–9