IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 71
IPSR-VIDEO
Manufacturer Part Number
IPSR-VIDEO
Description
RENEWAL Of IPS-VIDEO
Manufacturer
Altera
Series
IP Suitesr
Datasheet
1.IPS-VIDEO.pdf
(202 pages)
Specifications of IPSR-VIDEO
Software Application
IP CORE, SUITES
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Features
Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Lead Free Status / RoHS Status
na
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Chapter 4: Interfaces
Avalon-ST Video Protocol
Figure 4–12. Timing Diagram Showing R’G’B’ Transferred in Parallel
January 2011 Altera Corporation
dout_data
din_data
dout_startofpacket
dout_endofpacket
din_startofpacket
din_endofpacket
dout_ready
dout_valid
din_ready
din_valid
23:16
23:16
clock
15:8
15:8
7:0
7:0
In this case, both the input and output video data packets have a parallel color pattern
and eight bits per pixel per color plane as shown in
Table 4–8. Parameters for Example of Data Transferred in Parallel
Figure 4–12
This example has one Avalon-ST port named din and one Avalon-ST port named
dout. Data flows into the MegaCore function through din, is processed and flows out
of the MegaCore function through dout.
1.
2.
Bits per Pixel per Color Plane
shows how the first few pixels of a frame are processed.
Color Pattern
3.
Parameter
X
X
0
4.
G
R
B
0,0
0,0
0,0
5.
6.
G
B
R
X
X
0
1,0
1,0
1,0
7.
G
B
B
G
B
R
2,0
2,0
2,0
0,0
0,0
0,0
Table
Video and Image Processing Suite User Guide
4–8.
Value
R
G
8
B
n.
G
B
R
x,y
x,y
x,y
4–13
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