IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 176

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

6–20
Table 6–16. Scaler Signals (Part 2 of 2)
Scaler II
Table 6–17. Scaler II Signals (Part 1 of 2)
Video and Image Processing Suite User Guide
control_av_writedata
din_data
din_endofpacket
din_ready
din_startofpacket
din_valid
dout_data
dout_endofpacket
dout_ready
dout_startofpacket
dout_valid
Note to
(1) These ports are present only if Run-time control of image size is on in the parameter editor.
main_clock
main_reset
control_address
control_byteenable
Table 6–16
Signal
Signal
Table 6–17
Direction
In
In
In
Out
In
In
Out
Out
In
Out
Out
Direction
In
In
In
In
shows the input and output signals for the Scaler II MegaCore function.
control slave port Avalon-MM writedata bus. These input lines are used
for write transfers.
din port Avalon-ST data bus. Pixel data is transferred into the MegaCore
function over this bus.
din port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
din port Avalon-ST ready signal. This signal indicates when the MegaCore
function is ready to receive data.
din port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
din port Avalon-ST valid signal. This signal identifies the cycles when the
port should input data.
dout port Avalon-ST data bus. Pixel data is transferred out of the
MegaCore function over this bus.
dout port Avalon-ST endofpacket signal. This signal marks the end of an
Avalon-ST packet.
dout port Avalon-ST ready signal. This signal is asserted by the
downstream device when it is able to receive data.
dout port Avalon-ST startofpacket signal. This signal marks the start of
an Avalon-ST packet.
dout port Avalon-ST valid signal. This signal is asserted when the
MegaCore function outputs data.
The main system clock. The MegaCore function operates on the rising edge
of the main_clock signal.
The MegaCore function is asynchronously reset when main_reset is
asserted high. The reset must be deasserted synchronously with respect to
the rising edge of the main_clock_clk signal.
control slave port Avalon-MM address bus. Specifies a word offset into
the slave address space.
control slave port Avalon-MM byteenable bus. Enables specific byte
lane or lanes during transfers. Each bit in byteenable corresponds to a
byte in writedata and readdata. During reads, byteenable specifies
which bytes are being written to; other bytes are ignored by the slave.
During reads, byteenable indicates which bytes the master is reading.
Slaves that simply return readdata with no side effects are free to ignore
byteenable during reads.
(1)
(1)
(1)
Description
Description
January 2011 Altera Corporation
Chapter 6: Signals
Scaler II