IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 106

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

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Video and Image Processing Suite User Guide
Generator Lock
The mode registers can only be written to if a mode is marked as invalid. For example,
the following steps reconfigure mode 1:
1. Write 0 to the Mode1 Valid register.
2. Write to the mode 1 configuration registers.
3. Write 1 to the Mode1 Valid register. The mode is now valid and can be selected.
A currently-selected mode can be configured in this way without affecting the video
output of the MegaCore function.
When searching for a matching mode and there are multiple modes that match the
resolution, the function selects the lowest mode. For example, the function selects
Mode1 over Mode2 if they both match. To allow the function to select Mode2,
invalidate Mode1 by writing a 0 to its mode valid register. Invalidating a mode does
not clear its configuration.
Interrupts
The Clocked Video Output MegaCore function outputs a single interrupt line which is
the OR of the following internal interrupts:
■
■
Both interrupts can be independently enabled using bits [2:1] of the Control register.
The ir values can be read using bits [2:1] of the Interrupt register and a write of 1 to
either of these bits clears the respective interrupt.
The Clocked Video Output MegaCore function provides some functions to facilitate
Genlock. The MegaCore function can be configured to output, via the vcoclk_div
signal, a divided down version of its vid_clk (vcoclk) signal aligned to the SOF. By
setting the divided down value to be the length in samples of a video line, the
vcoclk_div signal can be configured to output a horizontal reference. The Genlock
functionality is enabled using the Control register. When Genlock functionality is
enabled the Clocked Video Output MegaCore does not synchronize itself to the
incoming Avalon-ST Video. Altera recommends that you disable Genlock
functionality before changing output mode and then only enable it again when the
status update interrupt has fired, indicating that the mode change has occurred.
The vcoclk_div signal can be compared to the refclk_div signal, output by a
Clocked Video Input MegaCore function, using a phase frequency detector (PFD) that
controls a voltage controlled oscillator (VCXO). By controlling the VCXO, the PFD can
align its output clock (vcoclk) to the reference clock (refclk). By tracking changes in
the refclk_div signal, the PFD can then ensure that the output clock is locked to the
incoming video clk.
The status update interrupt— Triggers when the Video Mode Match register is
updated by a new video mode being selected.
Locked interrupt—Triggers when the outgoing video SOF is aligned to the
incoming SOF.
Chapter 5: Functional Descriptions
January 2011 Altera Corporation
Clocked Video Output