IPSR-VIDEO Altera, IPSR-VIDEO Datasheet - Page 74

• Manufacturer Part Number: IPSR-VIDEO
• Description: RENEWAL Of IPS-VIDEO
• Manufacturer: Altera
• Series: IP Suitesr

Specifications of IPSR-VIDEO

• Software Application: IP CORE, SUITES
• Supported Families: Arria GX, Cyclone II, HardCopy II, Stratix II
• Features: Common Avalon Streaming (Avalon-St) Interface And Avalon-St Video Protocol
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–16
Video and Image Processing Suite User Guide
4. The MegaCore function sets dout_valid to logic '1' and outputs the blue color
5. The MegaCore function sets dout_valid to logic '0' and stops putting data on the
6. Both the input and output interfaces transfer no data: the MegaCore function is
7. The sink sets dout_ready to logic '1'. This could be because space has been cleared
8. The MegaCore function sets dout_valid to logic '1' and resumes transmitting data.
9. The source responds to din_ready by setting din_valid to logic '1' and resuming
Example 3 (Control Data Transfer)
Figure 4–14
field height 240). It is transferred over an interface configured for 10-bit data with two
color planes in parallel. Each word of the control packet is transferred in the lowest
four bits of a color plane, starting with bits 3:0, then 13:10.
value of the first processed color sample on the dout_data port. Simultaneously
the sink connected to the output port sets dout_ready to logic '0'. The
Interface Specifications
example because the sink is a FIFO and it has become full.
dout_data port because the sink is not ready for data. The MegaCore function also
sets din_ready to logic '0' because there is no way to output data and the
MegaCore function must stop the source from sending more data before it uses all
internal buffer space. The sink holds din_valid at logic '1' and transmits one more
color sample G
that the change in the MegaCore function's readiness does not take effect for one
clock cycle.
stalled waiting for the sink.
in a FIFO.
Now that the flow of data is again unimpeded, it sets din_ready to logic '1'.
data transfer.
shows the transfer of a control packet for a field of 720×480i video (with
m+1,n
, which is legal because the ready latency of the interface means
state that sinks may set ready to logic '0' at any time, for
January 2011 Altera Corporation
Avalon-ST Video Protocol
Chapter 4: Interfaces
Avalon